參數(shù)資料
型號: PC28F256J3C-125
廠商: INTEL CORP
元件分類: PROM
英文描述: Intel StrataFlash Memory (J3)
中文描述: 16M X 16 FLASH 2.7V PROM, 125 ns, PBGA64
封裝: LEAD FREE, BGA-64
文件頁數(shù): 49/72頁
文件大小: 905K
代理商: PC28F256J3C-125
256-Mbit J3 (x8/x16)
Datasheet
49
13.4
Array Protection
The V
PEN
signal is a hardware mechanism to prohibit array alteration. When the V
PEN
voltage is
below the V
PENLK
voltage, array contents cannot be altered. To ensure a proper erase or program
operation, V
PEN
must be set to a valid voltage level. To determine the status of an erase or program
operation, poll the Status Register and analyze the bits.
6
Factory
1
0
0
0
0
1
0
0
0
7
Factory
1
0
0
0
0
1
0
0
1
8
User
1
0
0
0
0
1
0
1
0
9
User
1
0
0
0
0
1
0
1
1
A
User
1
0
0
0
0
1
1
0
0
B
User
1
0
0
0
0
1
1
0
1
C
User
1
0
0
0
0
1
1
1
0
D
User
1
0
0
0
0
1
1
1
1
E
User
1
0
0
0
1
0
0
0
0
F
User
1
0
0
0
1
0
0
0
1
NOTE:
All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e.g., A[MAX:9] = 0.
Table 21. Byte-Wide Protection Register Addressing (Sheet 2 of 2)
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