參數(shù)資料
型號： PBL38773/1ML
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬傳輸電路
英文描述： TELECOM-SLIC, PQCC32
封裝： PLASTIC, VQFN-32
文件頁數(shù)： 58/64頁
文件大?。?/td> 1052K
代理商： PBL38773/1ML
Ringing FlexiSLIC
PBL 38773/1
Power-Up Sequence
Data Sheet
61
DS1, 2003-06-18
The line protection resistors
R
F1 and RF2 serve the dual purposes of being non-
destructing energy dissipators when transients are clamped and of being fuses when the
line is exposed to a power cross. If longitudinal balance requirements permit, PTC
resistors may be used for
R
F1 and RF2. Note, however, that it is important to use fixed
resistors in series with PTCs since PTCs are capacitive. Fast transients will therefore
experience much less PTC impedance than slower transients. Relying only on PTCs as
the current limiting element could therefore result in excessive fast transient current
through the clamp, with possible clamp current overload and resulting inability to protect
the SLIC. A value of approximately 40
for each of R
F1 and RF2 limits the peak
overvoltage transient current to a value that is compatible with the clamping device (OVP
block in Figure 8) capability. Higher resistance values for
R
F1 and RF2 than 40 will
require more stringent matching of the
R
F1 and RF2 resistors and will also have a much
greater impact on terminating impedance, gains and DC loop resistance. Lower
resistance values for
R
F1 and RF2 than 40 will result in peak clamp currents that may
exceed the capability of standard clamping devices.
13
Power-Up Sequence
No special power-up sequence is necessary except that ground has to be present before
all other power supply voltages. The digital inputs C1, C2 and C3 are internal pull-up
terminals.
14
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout is essential for proper function. The
components connection RSN input should be placed in close proximity to that pin, such
that no interference is injected into the receive summing node (RSN). Ground plane
surrounding the RSN pin is advisable. Analog Ground (AGND) should be connected to
Battery Ground (BGND) near the SLIC package.
R
LC and RREF should be connected to
AGND with short leads. Pin LP and HP are sensitive to leakage currents. The
C
LP
connection between pins LP and VTBAT should be as short as possible.
C
B and CTB
must be connected near the pins VBAT and VTBAT with short vias to ground. The TS
pin has to be connected to the TIPX pin with a short lead, ideal pins connected together.
The RS pin has to be connected to the RINGX pin with a short lead, ideal pins connected
together. The batwing pins, (SOIC) and exposed pad (MLP) are internally connected to
VBAT and used for transferring the heat from the chip to the printed circuit board. It is
therefore advisable to implement a PCB layout that facilitates heat conduction away from
the batwing pins.
相關(guān)PDF資料
PDF描述
PBL38773/1SO TELECOM-SLIC, PDSO28
PC-PVC-271K 1 ELEMENT, 270 uH, GENERAL PURPOSE INDUCTOR
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