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參數(shù)資料
| 型號： | PACVGA201QR |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | ROHS COMPLAINT, QSOP-16 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 93K |
| 代理商： | PACVGA201QR |
PACVGA201
Rev. 3 | Page 6 of 8 | www.onsemi.com
Application Information
Figure 1. Typical Connection Diagram
A resistor may be necessary between the V
CC2 pin and ground if protection against a stream of ESD pulses is
required while the PACVGA201 is in the power-down state. The value of this resistor should be chosen such
that the extra charge deposited into the V
CC2 bypass capacitor by each ESD pulse will be discharged before the
next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one
pulse per second. When the PACVGA201 is in the power-up state, an internal discharge resistor is connected
to ground via a FET switch for this purpose.
For the same reason, V
CC1 and VCC3 may also require bypass capacitor discharging resistors to ground if there
are no other components in the system to provide a discharge path to ground.
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