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參數(shù)資料
| 型號： | PACVGA201QR |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | ROHS COMPLAINT, QSOP-16 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 93K |
| 代理商： | PACVGA201QR |
PACVGA201
Rev. 3 | Page 5 of 8 | www.onsemi.com
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
CC1
V
CC1 Supply Current
V
CC1 = 5.0V
10
μA
V
CC3 = 5V; SYNC inputs at GND or VCC3;
PWR_UP pin at V
CC3; SYNC ouputs unloaded
10
μA
V
CC3 = 5V; SYNC inputs at 3.0V; PWR_UP
pin at V
CC3; SYNC ouputs unloaded
200
μA
I
CC3
V
CC3 Supply Current
V
CC3 = 5V; PWR_UP input at GND; SYNC
ouputs unloaded
10
μA
V
CC2
V
CC2 Pin Open Circuit
Voltage
V
CC2 voltage internally derived from VCC3 via
diode D1; no external current drawn
[V
CC3 -
0.80]
V
IH
Logic High Input Voltage
V
CC3 = 5V; Note 2
2.0
V
IL
Logic Low Input Voltage
V
CC3 = 5V; Note 2
0.8
V
OH
Logic High Output Voltage
I
OH = -4mA, VCC3 = 5.0V; Note 3
4.4
V
OL
Logic Low Output Voltage
I
OL = 4mA, VCC3 = 5.0V; Note 3
0.4
V
R
B, RP
Resistor Value
PWR_UP = V
CC3 = 5.0V
0.5
1
2
M
Ω
I
IN
Input Current
VIDEO_x pins
HSYNC, VSYNC pins
V
CC1 = 5.0V; VIN = VCC1 or GND
V
CC3 = 5.0V; VIN = VCC3 or GND
±1
μA
C
IN
Input Capacitance on
VIDEO_1, VIDEO_2 and
VIDEO_3 pins
V
CC1 = 5.0V; VIN = 2.5V; measured at 1MHz
V
CC1 = 2.5V; VIN = 1.25V; measured at 1MHz
4
4.5
pF
t
PLH
SYNC Buffer L => H
Propagation Delay
C
L = 50pF; VCC3 = 5.0V; Input tR and tF
≤ 5ns
8
12
ns
t
PHL
SYNC Buffer H => L
Propagation Delay
C
L = 50pF; VCC3 = 5.0V; Input tR and tF
≤ 5ns
8
12
ns
t
R, tF
SYNC Buffer Output Rise &
Fall Times
C
L = 50pF; VCC3 = 5.0V; Input tR and tF
≤ 5ns
7.0
ns
V
ESD
ESD Withstand Voltage
V
CC1 = VCC2 = VCC3 = 5V; Note 4
±8
kV
Note 1: All parameters specified over standard operating conditions unless otherwise noted.
Note 2: These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP.
Note 3: These parameters apply only to SYNC_OUT1 and SYNC_OUT2.
Note 4: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V
CC1, VCC2 and VCC3 must
be
bypassed to GND via a low impedance ground plane with a 0.2uF or greater, low inductance, chip ceramic capacitor at
each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative
with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2,
DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body
model (MIL-STD-883, Method 3015).
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