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參數(shù)資料
| 型號： | PA28F008SC-85 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 中文描述： | 1M X 8 FLASH 3.3V PROM, 85 ns, PDSO44 |
| 封裝： | 13.30 X 28.20 MM, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 466K |
| 代理商： | PA28F008SC-85 |
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28F008SA
PRINCIPLES OF OPERATION
The 28F008SA includes on-chip write automation to
manage write and erase functions. The Write State
Machine allows for 100% TTL-level control inputs,
fixed power supplies during block erasure and byte
write, and minimal processor overhead with RAM-
like interface timings.
After initial device powerup, or after return from
deep powerdown mode (see Bus Operations), the
28F008SA functions as a read-only memory. Manip-
ulation of external memory-control pins allow array
read, standby and output disable operations. Both
Status Register and intelligent identifiers can also be
accessed through the Command User Interface
when V
PP
e
V
PPL
.
This same subset of operations is also available
when high voltage is applied to the V
PP
pin. In addi-
tion, high voltage on V
PP
enables successful block
erasure and byte writing of the device. All functions
associated with altering memory contentsDbyte
write, block erase, status and intelligent identifierD
are accessed via the Command User Interface and
verified thru the Status Register.
Commands are written using standard microproces-
sor write timings. Command User Interface contents
serve as input to the WSM, which controls the block
erase and byte write circuitry. Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations. With the appropriate com-
mand written to the register, standard microproces-
sor read timings output array data, access the intelli-
gent identifier codes, or output byte write and block
erase status for verification.
Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the 28F008SA blocks. This code is copied to,
and executed from, system RAM during actual flash
memory update. After successful completion of byte
write and/or block erase, code/data reads from the
28F008SA are again possible via the Read Array
command. Erase suspend/resume capability allows
system software to suspend block erase to read
data and execute code from any other block.
FFFFF
64-Kbyte Block
EFFFF
F0000
64-Kbyte Block
DFFFF
E0000
64-Kbyte Block
CFFFF
D0000
64-Kbyte Block
BFFFF
C0000
64-Kbyte Block
AFFFF
B0000
64-Kbyte Block
9FFFF
A0000
64-Kbyte Block
8FFFF
90000
64-Kbyte Block
7FFFF
80000
64-Kbyte Block
6FFFF
70000
64-Kbyte Block
5FFFF
60000
64-Kbyte Block
4FFFF
50000
64-Kbyte Block
3FFFF
40000
64-Kbyte Block
2FFFF
30000
64-Kbyte Block
1FFFF
20000
64-Kbyte Block
0FFFF
10000
64-Kbyte Block
00000
Figure 6. Memory Map
Command User Interface and Write
Automation
An on-chip state machine controls block erase and
byte write, freeing the system processor for other
tasks. After receiving the Erase Setup and Erase
Confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
via the Status Register and RY/BY
Y
output. Byte
write is similarly controlled, after destination address
and expected data are supplied. The program and
erase algorithms of past Intel flash memories are
now regulated by the state machine, including pulse
repetition where required and internal verification
and margining of data.
9
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