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參數(shù)資料
| 型號(hào)： | PA28F008SC-85 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 中文描述： | 1M X 8 FLASH 3.3V PROM, 85 ns, PDSO44 |
| 封裝： | 13.30 X 28.20 MM, PLASTIC, SOP-44 |
| 文件頁(yè)數(shù)： | 4/33頁(yè) |
| 文件大?。?/td> | 466K |
| 代理商： | PA28F008SC-85 |
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28F008SA
Table 1. Pin Description
Symbol
Type
Name and Function
A
0
–A
19
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a write cycle.
DQ
0
–DQ
7
INPUT/OUTPUT
DATA INPUT/OUTPUTS:
Inputs data and commands during Command
User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.
CE
Y
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers,
decoders, and sense amplifiers. CE
Y
is active low; CE
Y
high deselects
the memory device and reduces power consumption to standby levels.
RP
Y
INPUT
RESET/DEEP POWERDOWN:
Puts the device in deep powerdown
mode. RP
Y
is active low; RP
Y
high gates normal operation. RP
Y
also
locks out block erase or byte write operations when active low, providing
data protection during power transitions. RP
Y
active resets internal
automation. Exit from Deep Powerdown sets device to read-array mode.
OE
Y
INPUT
OUTPUT ENABLE:
Gates the device’s outputs through the data buffers
during a read cycle. OE
Y
is active low.
WE
Y
INPUT
WRITE ENABLE:
Controls writes to the Command User Interface and
array blocks. WE
Y
is active low. Addresses and data are latched on the
rising edge of the WE
Y
pulse.
RY/BY
Y
OUTPUT
READY/BUSY
Y
:
Indicates the status of the internal Write State
Machine. When low, it indicates that the WSM is performing a block
erase or byte write operation. RY/BY
Y
high indicates that the WSM is
ready for new commands, block erase is suspended or the device is in
deep powerdown mode. RY/BY
Y
is always active and does
NOT
float
to tri-state off when the chip is deselected or data outputs are disabled.
V
PP
BLOCK ERASE/BYTE WRITE POWER SUPPLY
for erasing blocks of
the array or writing bytes of each block.
NOTE:
With V
PP
k
V
PPLMAX
, memory contents cannot be altered.
V
CC
DEVICE POWER SUPPLY (5V
g
10%, 5V
g
5%)
GND
GROUND
4
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| PA28F008SA-120 | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
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| PA34 | POWER OPERATIONAL AMPLIFIERS |
| PA44 | HIGH VOLTAGE POWER OPERATIONAL AMPLIFIER |
| PA7540JI-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
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