參數(shù)資料
型號(hào): P89V662FBC,557
廠商: NXP Semiconductors
文件頁(yè)數(shù): 54/90頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤(pán)
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱(chēng): 568-2435
568-2435-ND
568-8271
935280832557
P89V662FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
58 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP
bit enables the positive edge. If both bits are set both edges will be enabled and a capture
will occur for either transition.
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
Fig 27. PCA interrupt system
002aab914
PCA TIMER/COUNTER
MODULE0
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
MODULE1
MODULE2
MODULE3
MODULE4
ECF
ECCFn
IEN0.6
EC
IEN0.7
EA
CCAPMn.0
CMOD.0
CCON
(C0h)
to
interrupt
priority
decoder
Table 45.
CMOD - PCA counter mode register (address C1H) bit allocation
Not bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
CIDL
WDTE
-
CPS1
CPS0
ECF
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