參數(shù)資料
型號: P89V662FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 25/90頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2435
568-2435-ND
568-8271
935280832557
P89V662FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
31 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
STOP conditions are recognized as the beginning and end of a serial transfer. In a given
application, the I2C-bus may operate as a master and as a slave. In the slave mode, the
I2C-bus hardware looks for its own slave address and the general call address. If one of
these addresses is detected, an interrupt is requested. When the microcontrollers wishes
to become the bus master, the hardware waits until the bus is free before the master
mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost
in the master mode, the I2C-bus switches to the slave mode immediately and can detect
its own slave address in the same serial transfer.
Fig 12. Format of slave transmitter mode
S
R
A
slave address
logic 0 = write
logic 1 = read
from master to slave
from slave to master
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
002aaa933
DATA
data transferred
(n Bytes + acknowledge)
A
P
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