參數(shù)資料
型號: P89LPC938FDH
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable Flash with 10-bit A-D converter
封裝: P89LPC938FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;P89LPC938FHN<SOT788-1 (HVQFN28)|<<http://www.nxp.com/packages/SOT788-1.html&
文件頁數(shù): 20/68頁
文件大?。?/td> 318K
代理商: P89LPC938FDH
9397 750 14051
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2005
27 of 68
Philips Semiconductors
P89LPC938
8-bit microcontroller with 10-bit A/D converter
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
7.16 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,
P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-up sequence, The RPE selection is overridden and this pin will
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as dened by the RPE bit. Only a power-up reset will temporarily override the selection
dened by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
External reset pin (during power-up or if user congured via UCFG1);
Power-on detect;
Brownout detect;
Watchdog timer;
Software reset;
UART break character detect reset.
For every reset source, there is a ag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These ag bits can be cleared in
software by writing a ‘0’ to the corresponding bit. More than one ag bit may be set:
During a power-on reset, both POF and BOF are set but the other ag bits are
cleared.
For any other reset, previously set ag bits that have not been cleared will remain set.
7.16.1 Reset vector
Following reset, the P89LPC938 will fetch instructions from either address 0000h or the
Boot address. The Boot address is formed by using the Boot Vector as the high byte of the
address and the low byte of the address = 00h.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC938 User’s Manual). Otherwise, instructions will be fetched from address 0000H.
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