參數(shù)資料
型號(hào)： P89LPC938FA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable Flash with 10-bit A/D converter
中文描述： 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PQCC28
封裝： PLASTIC, MS-018, SOT-261-2, LCC-28
文件頁(yè)數(shù)： 53/68頁(yè)
文件大小： 318K
代理商： P89LPC938FA
9397 750 14051
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2005
53 of 68
Philips Semiconductors
P89LPC938
8-bit microcontroller with 10-bit A/D converter
11. Dynamic characteristics
Table 11:
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1] [2]
Symbol
Parameter
AC characteristics
Conditions
Variable clock
Min
7.189
320
0
83
0
f
osc
= 12 MHz
Min
7.189
320
-
-
-
Unit
Max
7.557
520
12
-
8
Max
7.557
520
-
-
-
f
OSC(RC)
f
OSC(WD)
f
osc
T
cy(CLK)
f
CLKLP
Glitch filter
t
gr
internal RC oscillator frequency
internal watchdog oscillator frequency
oscillator frequency
clock cycle time
low power select frequency
MHz
kHz
MHz
ns
MHz
see
Figure 23
glitch rejection
P1.5/RST pin
anypinexcept
P1.5/RST
P1.5/RST pin
anypinexcept
P1.5/RST
-
-
50
15
-
-
50
15
ns
ns
t
sa
signal acceptance
125
50
-
-
125
50
-
-
ns
ns
External clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising edge
time
t
XHQX
output data hold after clock rising
edge time
t
XHDX
input data hold after clock rising edge
time
t
XHDV
input data valid to clock rising edge
time
SPI interface
f
SPI
SPI operating frequency
2.0 MHz (slave)
3.0 MHz (master)
t
SPICYC
SPI cycle time
2.0 MHz (slave)
3.0 MHz (master)
t
SPILEAD
SPI enable lead time
2.0 MHz (slave)
t
SPILAG
SPI enable lag time
2.0 MHz (slave)
clock HIGH time
clock LOW time
clock rise time
clock fall time
see
Figure 23
see
Figure 23
see
Figure 23
see
Figure 23
33
33
-
-
T
cy(CLK)
t
CLCX
33
T
cy(CLK)
t
CHCX
33
8
8
-
-
8
8
ns
ns
ns
ns
-
-
see
Figure 22
see
Figure 22
16 T
cy(CLK)
-
13 T
cy(CLK)
-
1333
1083
-
-
ns
ns
see
Figure 22
-
T
cy(CLK)
+ 20
-
103
ns
see
Figure 22
-
0
-
0
ns
see
Figure 22
150
-
150
-
ns
0
-
CCLK
6
CCLK
4
0
-
2.0
3.0
MHz
MHz
see
Figure 24
,
25
,
26
,
27
6
CCLK
4
CCLK
-
-
500
333
-
-
ns
ns
see
Figure 26
,
27
250
-
250
-
ns
see
Figure 26
,
27
250
-
250
-
ns
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