參數(shù)資料
型號: P89LPC938FA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable Flash with 10-bit A/D converter
中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PQCC28
封裝: PLASTIC, MS-018, SOT-261-2, LCC-28
文件頁數(shù): 33/68頁
文件大?。?/td> 318K
代理商: P89LPC938FA
9397 750 14051
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2005
33 of 68
Philips Semiconductors
P89LPC938
8-bit microcontroller with 10-bit A/D converter
7.20.3
Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). When data is
transmitted, the 9
th
data bit (TB8 in SCON) can be assigned the value of ‘0’ or ‘1’. Or, for
example, the parity bit (P, in the PSW) could be moved into TB8. When data is received,
the 9
th
data bit goes into RB8 in Special Function Register SCON, while the stop bit is not
saved. The baud rate is programmable to either
1
16
or
1
32
of the CPU clock frequency, as
determined by the SMOD1 bit in PCON.
7.20.4
Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 7.20.5 “Baud rate generator and selection”
).
7.20.5
Baud rate generator and selection
The P89LPC938 enhanced UART has an independent Baud Rate Generator. The baud
rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see
Figure 12
). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.
7.20.6
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is ‘1’, framing errors can be made available in SCON.7 respectively. If SMOD0 is ‘0’,
SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when
SMOD0 is ‘0’.
7.20.7
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
Fig 12. Baud rate sources for UART (Modes 1, 3).
baud rate modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
002aaa897
÷
2
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