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參數(shù)資料
| 型號： | P89LPC932FDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB Flash with 512-byte data EEPROM and 768-byte RAM |
| 中文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-361-1, TSSOP-28 |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 316K |
| 代理商： | P89LPC932FDH |
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9397 750 14871
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 10 May 2005
34 of 64
Philips Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.21 I
2
C-bus serial interface
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
Bi-directional data transfer between masters and slaves.
Multi master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus may be used for test and diagnostic purposes.
A typical I
2
C-bus configuration is shown in
Figure 13
. The P89LPC932A1 device provides
a byte-oriented I
2
C-bus interface that supports data transfers up to 400 kHz.
Fig 13. I
2
C-bus configuration.
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
SDA
SCL
R
P
R
P
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
P1.3/SDA
P89LPC932A1
P1.2/SCL
I
2
C-bus
002aaa898
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