參數(shù)資料
型號(hào)： P89LPC932FDH
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB Flash with 512-byte data EEPROM and 768-byte RAM
中文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO28
封裝： 4.40 MM, PLASTIC, MO-153, SOT-361-1, TSSOP-28
文件頁(yè)數(shù)： 28/64頁(yè)
文件大?。?/td> 316K
代理商： P89LPC932FDH
9397 750 14871
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 10 May 2005
28 of 64
Philips Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.19 CCU
This unit features:
A 16-bit timer with 16-bit reload on overflow.
Selectable clock, with prescaler to divide clock source by any integral number
between 1 and 1024.
Four Compare/PWM outputs with selectable polarity
Symmetrical/Asymmetrical PWM selection
Two Capture inputs with event counter and digital noise rejection filter
Seven interrupts with common interrupt vector (one Overflow, two Capture,
four Compare)
Safe 16-bit read/write via shadow registers.
7.19.1
CCU clock
The CCU runs on the CCU Clock (CCUCLK), which is either PCLK in basic timer mode, or
the output of a Phase-Locked Loop (PLL). The PLL is designed to use a clock source
between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between
16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a
4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.
7.19.2
CCUCLK prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow.
7.19.3
Basic timer operation
The Timer is a free-running up/down counter with a direction control bit. If the timer
counting direction is changed while the counter is running, the count sequence will be
reversed. The timer can be written or read at any time.
When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt
generated if enabled. The 16-bit CCU Timer may also be used as an 8-bit up/down timer.
7.19.4
Output compare
There are four output compare channels A, B, C and D. Each output compare channel
needs to be enabled in order to operate and the user will have to set the associated I/O
pin to the desired output mode to connect the pin. When the contents of the timer matches
that of a capture compare control register, the Timer Output Compare Interrupt Flag
(TOCFx) becomes set. An interrupt will occur if enabled.
7.19.5
Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register. The capture event can be programmed to be either rising or falling edge
triggered. A simple noise filter can be enabled on the input capture by enabling the Input
Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of
the same value in order to recognize an edge as a capture event. An event counter can be
set to delay a capture by a number of capture events.
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