參數(shù)資料
型號: P89LPC932FDH
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB Flash with 512-byte data EEPROM and 768-byte RAM
中文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO28
封裝: 4.40 MM, PLASTIC, MO-153, SOT-361-1, TSSOP-28
文件頁數(shù): 30/64頁
文件大小: 316K
代理商: P89LPC932FDH
9397 750 14871
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 10 May 2005
30 of 64
Philips Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.19.7
Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
7.19.8
PLL operation
The PWM module features a PLL that can be used to generate a CCUCLK frequency
between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic
PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or
higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output
signal of 32 times the input frequency. This signal is used to clock the timer. The user will
have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the
SFR register TCR21. The PLL frequency can be expressed as shown in
Equation 1
.
N
1
+
)
(1)
Where: N is the value of PLLDV3:0.
Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to
PCLK
16
.
Fig 10. Alternate output mode.
TIMER VALUE
002aaa895
0
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
PWM OUTPUT A (or C) (P2.6)
PWM OUTPUT B (or D) (P1.6)
PLL frequency
------------------
=
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