參數(shù)資料
型號： P89LPC932BA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller with two-clock core 8 KB 3 V low-power Flash with 512-byte data EEPROM
中文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQCC28
封裝： PLASTIC, MS-018, SOT-261-2, LCC-28
文件頁數(shù)： 41/64頁
文件大?。?/td> 316K
代理商： P89LPC932BA
9397 750 14871
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 10 May 2005
41 of 64
Philips Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.25 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog feature is disabled, it can be used as an interval timer
and may generate an interrupt.
Figure 20
shows the watchdog timer in Watchdog mode.
Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog
clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a
time-out period that ranges from a few
μ
s to a few seconds. Please refer to the
P89LPC932A1 User manualfor more details.
7.26 Additional features
7.26.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.26.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 20. Watchdog timer in Watchdog mode (WDTE = 1).
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
WDCON (A7H)
SHADOW REGISTER
PRESCALER
002aaa905
8-BIT DOWN
COUNTER
WDL (C1H)
watchdog
oscillator
PCLK
÷
32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
reset
(1)
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