參數(shù)資料
型號(hào)： P89LPC932BA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller with two-clock core 8 KB 3 V low-power Flash with 512-byte data EEPROM
中文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQCC28
封裝： PLASTIC, MS-018, SOT-261-2, LCC-28
文件頁數(shù)： 19/64頁
文件大小： 316K
代理商： P89LPC932BA
9397 750 14871
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 10 May 2005
19 of 64
Philips Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
The frequency of this clock output is
1
2
that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC932A1 has a 6-bit TRIM register that can be used to tune the frequency of
the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed
value to adjust the oscillator frequency to 7.373 MHz
±
1 % at room temperature.
End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to
other frequencies.
7.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the
XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin may be
used as a standard port pin or a clock output.
When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until V
DD
has reached its
specified level. When system power is removed V
DD
will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when V
DD
falls below the minimum specified operating voltage.
Fig 6.
Block diagram of oscillator control.
÷
2
002aaa891
RTC
CPU
WDT
DIVM
CCLK
UART
OSCCLK
I
2
C-BUS
PCLK
TIMER 0 AND
TIMER 1
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC
OSCILLATOR
WATCHDOG
OSCILLATOR
(7.3728 MHz
±
1 %)
PCLK
RCCLK
SPI
CCU
(P89LPC932A1)
32
×
PLL
(400 kHz 30 %
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