參數(shù)資料
型號: P89LPC917
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V Flash with 8-bit A/D converter
中文描述: 8 - 8加速雙位單片機80C51的時鐘核心2 Kb的3伏閃存位A / D轉(zhuǎn)換器
文件頁數(shù): 14/72頁
文件大?。?/td> 344K
代理商: P89LPC917
Philips Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 04 — 17 December 2004
14 of 72
9397 750 14397
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P1.0 to P1.5
I/O
(P1.2);
I (P1.5)
Port 1:
Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the outputs depends upon the port configuration selected. Refer to
Section 9.12.1 “Port configurations”
and
Table 13 “DC electrical characteristics”
for
details. P1.2 and P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0 —
Port 1 bit 0.
TxD —
Serial port transmitter data.
P1.1 —
Port 1 bit 1.
RxD —
Serial port receiver data.
P1.2 —
Port 1 bit 2. (Open drain when used as an output.)
T0 —
Timer/counter 0 external count input, overflow, or PWM output.
SCL —
I
2
C-bus serial clock input/output.
P1.3 —
Port 1 bit 3. (Open drain when used as an output.)
INT0 —
External interrupt 0 input.
SDA —
I
2
C-bus serial data input/output.
P1.4 —
Port 1 bit 4.
INT1 —
External interrupt 1input.
P1.5 —
Port 1 bit 5. (Input only.)
RST —
External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0.
When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V
DD
has reached its specified level.
When system power is removed V
DD
will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when V
DD
falls below the minimum specified operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
Port 2:
Port 2.2 is a single-bit I/O port with a user-configurable output. During reset
the Port 2.2 latch is configured in the input only mode with the internal pull-up
disabled. The operation of the output depends upon the port configuration selected.
Refer to
Section 9.12.1 “Port configurations”
and
Table 13 “DC electrical
characteristics”
for details.
This pin has a Schmitt triggered input.
Ground:
0 V reference.
Power Supply:
This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
10
I/O
O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
9
8
7
6
3
P2.2
5
I/O
V
SS
V
DD
4
12
I
I
Table 5:
Symbol
P89LPC917 pin description
…continued
Pin
Type
Description
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