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| 型號： | P89CE558EFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-chip 8-bit microcontroller |
| 中文描述： | FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數(shù)： | 41/72頁 |
| 文件大?。?/td> | 721K |
| 代理商： | P89CE558EFB |
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Philips Semiconductors
Preliminary specification
P83CE558/P80CE558/P89CE558
Single-chip 8-bit microcontroller
1996 Aug 06
41
Figure 39. Power control register (PCON).
7
6
5
4
3
2
1
0
PCON (87H)
SMOD
ARD
RFI
WLE
GF1
GF0
PD
IDL
Table 39.
Description of PCON bits
SYMBOL
BIT
FUNCTION
SMOD
PCON.7
Double Baud rate bit. When set to logic 1 the baud rate is doubled when the serial port SIO0 is being used in
modes 1, 2, or 3.
ARD
PCON.6
AUX-RAM disable bit. When set to a 1 the internal 768 bytes AUX-RAM is disabled, so that all
MOVX-Instructions access the external data memory – as it is with the standard PCB80C51.
RFI
PCON.5
Reduced radio frequency interference bit. When set to a 1 the toggling of ALE pin is prohibited. This bit is
cleared on RESET (see also sections Features (EMC) and Pinning).
WLE
PCON.4
Watchdog load enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is cleared
when timer T3 is loaded.
GF1
PCON.3
General-purpose flag bit
GF0
PCON.2
General-purpose flag bit
PD
PCON.1
Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high.
IDL
PCON.0
Idle Mode bit. Setting this bit activates the Idle Mode.
6.11
Two software-selectable modes of reduced power consumption are
implemented. These are the Idle Mode and the Power-down Mode.
Power Reduction Modes
Idle Mode operation permits the interrupt, serial ports and timer
blocks T0, T1 and T3 to function while the CPU is halted. The
following functions are switched off when the microcontroller enters
the Idle Mode:
CPU
(halted)
Timer 2
(stopped and reset)
PWM0, PWM1
(reset, output = HIGH)
ADC
(aborted if conversion in progress)
The following functions remain active during Idle Mode. These
functions may generate an interrupt or reset and thus terminate the
Idle Mode:
Timer 0, Timer 1, Timer 3 (Watchdog timer)
UART
I
2
C
External interrupt
Seconds Timer
In Power-down Mode the system clock is halted. If the PLL oscillator
is selected (SELXTAL1 = 0) and the RUN32 bit is set, the 32 kHz
oscillator keeps running, otherwise it is stopped. If the HF-oscillator
(SELXTAL1 = 1) is selected, it is stopped after setting the bit PD in
the PCON register.
Table 40.
External Pin Status During Idle and Power-Down Modes
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
SCL/SDA
PWM0/PWM1
Idle
Internal
1
1
data
data
data
data
data
operative (1)
HIGH
Idle
External
1
1
high-Z
data
address
data
data
operative (1)
HIGH
Power-down
Internal
0
0
data
data
data
data
data
high-Z
HIGH
Power-down
NOTE:
1. In Idle Mode SCL and SDA can be active as outputs only if SIO1 is enabled; if SIO1 is disabled (S1CON.6/ENS1 = 0) these pins are in a
high-impedance state.
External
0
0
high-Z
data
data
data
data
high-Z
HIGH
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