參數(shù)資料
型號(hào)： P87CE560EFB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： BATTERY CHG UNIV 12VDC @ 500MA
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 X 2.70 MM, PLASTIC, SOT-318-1, QFP-80
文件頁(yè)數(shù)： 40/84頁(yè)
文件大?。?/td> 441K
代理商： P87CE560EFB
1997 Aug 01
40
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
14 INTERRUPT SYSTEM
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. Interrupt response
time in a single-interrupt system is in the range
2.25
μ
s to 6.75
μ
s when using a 16 MHz crystal.
The latency time depends on the sequence of instructions
executed directly after an interrupt request.
The P8xCE560 acknowledges interrupt requests from
15 sources as follows (see Fig.14):
INT0 and INT1 external interrupts
Timer 0 and Timer 1 internal timer/counter interrupts
Timer 2 internal timer/counter byte and/or 16-bit
overflow, 3 compare and 4 capture interrupts (or
4 additional external interrupts).
Note that if a capture register is unused and its contents
are of no interest, then the corresponding input pin
CTnI/P1.n (n = 0 to 3) may be used as a (configurable)
positive and/or negative edge triggered additional
external interrupt input (INT2, INT3, INT4 and INT5).
UART serial I/O port receive/transmit interrupt
I
2
C-bus interface serial I/O interrupt
ADC autoscan completion interrupt
‘Seconds’ timer interrupt SEC (ORed with INT1); for
details please refer to Chapter 16.2.4.
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in register TCON. The flags that actually
generate these interrupts are bits IE0 and IE1 in TCON.
When an external interrupt is generated, the
corresponding request flag is cleared by the hardware
when the service routine is vectored to, only if the interrupt
was transition-activated. If the interrupt was level-activated
then the interrupt request flag remains set until the external
interrupt pin INTn goes HIGH. Consequently, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate
the request before the interrupt service routine is
completed, or else another interrupt will be generated.
As these external interrupts are active LOW a ‘wire-ORing’
of several interrupt sources to one input pin allows
expansion.
The Timer 0 and Timer 1 interrupts are generated by TF0
and TF1, which are set by a roll-over in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a Timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
The eight Timer/Counter T2 Interrupt sources are:
4 capture Interrupts (1), 3 compare interrupts and an
overflow interrupt. The appropriate interrupt request flags
must be cleared by software.
The UART Serial Port Interrupt is generated by the logical
OR of RI and TI (register S0CON). Neither of these flags
is cleared by hardware. The service routine will normally
have to determine whether it was RI or TI that generated
the interrupt, and the bit will have to be cleared by
software.
The I
2
C Interrupt is generated by bit SI in register S1CON.
This flag has to be cleared by software.
The ADC Interrupt is generated by bit ADINT, which is set
when the conversion of all selected analog inputs to be
scanned is finished. ADINT must be cleared by software.
It cannot be set by software.
The ‘seconds’ timer Interrupt is generated by bit SECINT
in register PLLCON. This flag has to be cleared by
software. Note that the ‘seconds’ timer can only be used
with the 32 kHz PLL oscillator.
All of the bits that generate interrupts can be set or cleared
by software, with the same result as though they had been
set or cleared by hardware (except the ADC interrupt
request flag ADINT, which cannot be set by software).
That is, interrupts can be generated or pending interrupts
can be cancelled in software.
The Interrupts X0, T0, X1, T1, SEC, S0 and S1 are able to
terminate the Idle mode.
14.1
Interrupt Enable Registers
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in the interrupt enable
Special Function Registers IEN0 and IEN1. All interrupt
sources can also be globally disabled by clearing bit EA in
IEN0. The interrupt enable registers are described in
Tables 62 and 64.
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