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參數(shù)資料
| 型號： | P87CE560EFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | BATTERY CHG UNIV 12VDC @ 500MA |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁數(shù)： | 16/84頁 |
| 文件大?。?/td> | 441K |
| 代理商： | P87CE560EFB |
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1997 Aug 01
16
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
9
I/O FACILITIES
The P8xCE560 has six 8-bit ports. Ports 0 to 3 are the
same as in the 80C51, with the exception of the additional
functions of Port 1. The parallel I/O function of Port 4 is
equal to that of Ports 1, 2 and 3. All ports are bidirectional
with the exception of Port 5 which is only a parallel input
port.
Ports 0, 1, 2, 3, 4 and 5 perform the following alternative
functions:
Port 0 Provides the multiplexed low-order address and
data bus used for expanding the P8xCE560 with
standard memories and peripherals.
Port 1 Is used for a number of special functions:
4 capture inputs (or external interrupt request
inputs if capture information is not utilized)
external counter input
external counter reset input.
Port 2 Provides the high-order address bus when the
P8xCE560 is expanded with external Data Memory
and / or the P8xCE560 executes from external
Program Memory.
Port 3 Pins can be configured individually to provide:
External interrupt request inputs
Counter inputs
Receiver input and transmitter output of serial
port SIO 0 (UART)
Control signals to read and write external Data
Memory.
Port 4 Can be configured to provide signals indicating a
match between timer/counter T2 and its compare
registers.
Port 5 May be used in conjunction with the ADC interface.
Unused analog inputs can be used as digital inputs.
As Port 5 lines may be used as inputs to the ADC,
these digital inputs have an inherent hysteresis to
prevent the input logic from drawing too much
current from the power lines when driven by analog
signals. Channel-to-channel crosstalk should be
taken into consideration when both digital and
analog signals are simultaneously input to Port 5
(see Chapter 21).
A pin of which the alternative function is not used may be
used as normal bidirectional I/O. The generation or use of
a Port 1, Port 3 or Port 4 pin as an alternative function is
carried out automatically by the P8xCE560 provided the
associated Special Function Register bit is set HIGH.
The SDA and SCL lines serve the serial port SI01
(I
2
C-bus). Because the I
2
C-bus may be active while the
device is disconnected from V
DD
, these pins are provided
with open-drain drivers.
Figure 8 shows the pull-up arrangements of Ports 1 to 4;
Transistor ‘p1’ is turned on for 2 oscillator periods after Q
makes a HIGH-to-LOW transition. During this time, ‘p1’
also turns on ‘p3’ through the inverter to form an additional
pull-up.
Fig.8 I/O buffers in the P8xCE560 (Port 1 to Port 4).
handbook, full pagewidth
MLC926 - 1
p1
p2
p3
input data
read port pin
2 oscillator
periods
n
strong pull-up
I/O PIN
V
I1
Q
from port latch
INPUT
BUFFER
DD
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