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參數(shù)資料
| 型號(hào)： | P87CE560EFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | BATTERY CHG UNIV 12VDC @ 500MA |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁(yè)數(shù)： | 33/84頁(yè) |
| 文件大?。?/td> | 441K |
| 代理商： | P87CE560EFB |
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1997 Aug 01
33
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
13.1.1
S
ERIAL
P
ORT
C
ONTROL
R
EGISTER
(S0CON)
Table 43
Serial Port Control Register (address 98H)
Table 44
Description of S0CON bits
Table 45
Serial port mode select
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
BIT
SYMBOL
DESCRIPTION
7
6
5
SM0
SM1
SM2
These bits are used to select the serial port mode; see Table 45.
Enables the multiprocessor communication feature in Modes 2 and 3. In these modes,
if SM2 = 1, then RI will not be activated if the received 9
th
data bit (RB8) is a logic 0.
In Mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received.
In Mode 0, SM2 should be a logic 0.
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception.
The 9
th
data bit that will be transmitted in modes 2 and 3. Set or clear by software as
desired.
In modes 2 and 3, RB8 is the 9
th
data bit that was received. In Mode 1, if SM2 = 0, RB8
is the stop bit that was received. In Mode 0, RB8 is not used.
Transmit Interrupt flag
. Set by hardware at the end of the 8
th
bit time in Mode 0, or at
the beginning of the stop bit in the other modes, in any serial transmission. Must be
cleared by software.
Receive Interrupt flag
. Set by hardware at the end of the 8
th
bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception (except
see SM2). Must be cleared by software.
4
REN
3
TB8
2
RB8
1
TI
0
RI
SM0
SM1
MODE
DESCRIPTION
BAUD RATE
0
0
1
1
0
1
0
1
Mode 0
Mode 1
Mode 2
Mode 3
Shift register
8-bit UART
9-bit UART
9-bit UART
1
12
×
f
clk
variable
1
64
or
1
32
×
f
clk
variable
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