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參數(shù)資料
| 型號： | P87CE560EFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | BATTERY CHG UNIV 12VDC @ 500MA |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁數(shù)： | 17/84頁 |
| 文件大小： | 441K |
| 代理商： | P87CE560EFB |
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1997 Aug 01
17
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
10 PULSE WIDTH MODULATED OUTPUTS
The P8xCE560 contains two Pulse Width Modulated
(PWM) output channels (see Fig.9). These channels
generate pulses of programmable length and interval.
The repetition frequency is defined by an 8-bit prescaler
PWMP, which supplies the clock for the counter.
The prescaler and counter are common to both PWM
channels. The 8-bit counter counts modulo 255, i.e., from
0 to 254 inclusive. The value of the 8-bit counter is
compared to the contents of two registers: PWM0 and
PWM1.
Provided the contents of either of these registers is greater
than the counter value, the corresponding PWM0 or
PWM1 output is set LOW. If the contents of these registers
are equal to, or less than the counter value, the output will
be HIGH. The pulse-width-ratio is therefore defined by the
contents of the registers PWM0 and PWM1.
The pulse-width-ratio is in the range of
0
255
to
255
255
and
may be programmed in increments of
1
255
.
Buffered PWM outputs may be used to drive DC motors.
The rotation speed of the motor would be proportional to
the contents of PWMn. The PWM outputs may also be
configured as a dual DAC.
In this application, the PWM outputs must be integrated
using conventional operational amplifier circuitry. If the
resulting output voltages have to be accurate, external
buffers with their own analog supply should be used to
buffer the PWM outputs before they are integrated.
The repetition frequency f
PWM
, at the PWMn outputs is
given by:
This gives a repetition frequency range of 123 Hz to
31.4 kHz (at f
clk
= 16 MHz). By loading the PWM registers
with either 00H or FFH, the PWM channels will output a
constant HIGH or LOW level, respectively. Since the 8-bit
counter counts modulo 255, it can never actually reach the
value of the PWM registers when they are loaded with
FFH.
When a compare register (PWM0 or PWM1) is loaded with
a new value, the associated output is updated
immediately. It does not have to wait until the end of the
current counter period. Both PWMn output pins are driven
by push-pull drivers. These pins are not used for any other
purpose.
f
PWM
f
2
PWMP
1
+
(
)
×
255
×
---------------------------------------------------------------
=
Fig.9 Functional diagram of Pulse Width Modulated outputs.
handbook, full pagewidth
MGA154
I
N
T
E
R
N
A
L
B
U
S
fclk
PWMP
PWM1
PRESCALER
8-BIT COUNTER
1/2
PWM0
8-BIT COMPARATOR
8-BIT COMPARATOR
OUTPUT
BUFFER
PWM1
OUTPUT
BUFFER
PWM0
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