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參數(shù)資料
| 型號： | P87CE560 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 64/84頁 |
| 文件大?。?/td> | 441K |
| 代理商： | P87CE560 |
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1997 Aug 01
64
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
Notes to the DC characteristics
1.
See Figs 22, 25 and 24 for I
DD
test conditions.
2.
The operating supply current is measured with all output pins disconnected; XTAL1 driven with
t
r
= t
f
= 5ns; V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2, XTAL3 not connected;
Port 0 = EW = SCL = SDA = SELXTAL1 = V
DD
; EA = RSTIN = ADEXS = XTAL4 = V
SS
.
3.
The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5ns;
V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2, XTAL3 not connected;
EA = RSTIN = Port 0 = EW = SCL = SDA = SELXTAL1 = V
DD
; ADEXS = XTAL4 = V
SS
.
4.
The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
Port 0 = EW = SCL = SDA = SELXTAL1 = V
DD
; EA = RSTIN = ADEXS = XTAL1 = XTAL4 = V
SS
.
5.
The input threshold voltage of SCL and SDA (SIO1) meets the I
2
C specification, so an input voltage below 0.3 V
DD
will be recognized as a logic 0 while an input voltage above 0.7 V
DD
will be recognized as a logic 1.
6.
Pins of Ports 1, 2, 3 and 4 source a transition current when they are being externally driven from HIGH to LOW.
The transition current reaches its maximum value when V
IN
is approximately 2 V.
7.
Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
of ALE and Ports 1, 3
and 4. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make
HIGH-to-LOW transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on
the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an
address latch with a Schmitt Trigger STROBE input.
8.
Capacitive loading on Ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9 V
DD
specification when the address bits are stabilizing.
9.
V
ref(n)(A)
= 0 V; V
DDA
= 5.0 V, V
ref(p)(A)
= 5.12 V. V
DD
= 5.0 V, V
SS
= 0 V, ADC is monotonic with no missing codes.
Measurement by continuous conversion of V
in(A)
=
20 mV to 5.12 V in steps of 0.5 mV, deriving parameters from
collected conversion results of ADC. ADC prescaler programmed according to the actual oscillator frequency,
resulting in a conversion time within the specified range for t
ADC
(15 to 50
μ
s).
10. The differential non-linearity (D
Le
) is the difference between the actual step width and the ideal step width.
11. The ADC is monotonic; there are no missing codes.
12. The integral non-linearity (I
Le
) is the peak difference between the centre of the steps of the actual and the ideal
transfer curve after appropriate adjustment of gain and offset error.
13. The offset error (OS
e
) is the absolute difference between the straight line which fits the actual transfer curve (after
removing gain error), and a straight line which fits the ideal transfer curve. The offset error is constant at every point
of the actual transfer curve.
14. The gain error (G
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after
removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point
on the transfer curve.
15. The absolute voltage error (A
e
) is the maximum difference between the centre of the steps of the actual transfer curve
of the non-calibrated ADC and the ideal transfer curve.
16. This should be considered when both analog and digital signals are simultaneously input to Port 5.
17. The supply current with 32 kHz oscillator running and PLL operation (SELXTAL1 = 0) is measured with all output
pins disconnected; XTAL4 driven with t
r
= t
f
= 5 ns; V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected;
Port 0 = EW = SCL = SDA = V
DD
; EA = RSTIN = ADEXS = SELXTAL 1 = XTAL1 = V
SS
.
18. Not 100% tested; sum of I
DDA(ID)
(PLL) and I
DDA
(HF-Oscillator).
19. The parameter meets the I
2
C-bus specification for standard-mode and fast-mode devices.
20. Not 100% tested.
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