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參數(shù)資料
| 型號： | P87CE560 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 31/84頁 |
| 文件大?。?/td> | 441K |
| 代理商： | P87CE560 |
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1997 Aug 01
31
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
12.3
Watchdog Timer (T3)
In addition to Timer T2 and the standard timers, a
Watchdog Timer (T3) consisting of an 11-bit prescaler and
an 8-bit timer is also incorporated (see Fig.12).
T3 is incremented every 1.5 ms, derived from the oscillator
frequency of 16 MHz by the following formula:
f
2048
×
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at pin RSTOUT. Also
the PLL control register is reset.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control.
f
timer
12
=
The Watchdog Timer can only be reloaded if the condition
flag WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer’s reloading and the
occurrence of a reset depends on the reloaded value.
For example, this may range from 1.5 ms to 0.375 s when
using an oscillator frequency of 16 MHz.
In the Idle state the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer is controlled by the watchdog enable
pin (EW). A LOW level enables the watchdog timer and
disables the Power-down mode. A HIGH level disables the
watchdog timer and enables the Power-down mode.
Fig.12 Functional diagram of T3 Watchdog Timer.
handbook, full pagewidth
MBH081
INTERNAL BUS
1/12 fclk
write
T3
PRESCALER
11-BIT
TIMER T3 (8-BIT)
LOAD
CLEAR
to reset circuitry
LOADEN
EW
LOADEN
PCON.4
PCON.1
CLEAR
WLE
PD
INTERNAL BUS
(1)
(1) See Fig.20.
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