參數(shù)資料
型號(hào)： P87CE560
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 8位微控制器
英文描述： 8-BIT SINGLE CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 24/84頁(yè)
文件大小： 441K
代理商： P87CE560
1997 Aug 01
24
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
Table 23
Prescaler selection
11.8.4
D
IGITAL
I
NPUT
P
ORT
R
EGISTER
(P5)
Digital Input Port Register (P5) is shared with analog inputs. P5 is not affected by chip reset. SFR P5 always represents
the binary value of the logic level at input pins P5.0/ADC0 to P5.7/ADC7. Reading P5 does not affect analog-to-digital
conversions. But it is recommended to use the digital input port function of the hardware Port 5 only as an alternative to
analog input voltage conversions. Simultaneous mixed operation is discouraged to guarantee a reliable and accurate
ADC result. For more information on P5 refer to Chapter 9.
Table 24
Digital Input Port Register (address C7H)
Table 25
Description of P5 bits
3
ADSST
ADC start and status.
Setting this bit by software or by hardware (via ADEXS input)
starts the analog-to-digital conversion of the selected analog inputs. ADSST stays a
logic 1 in continuous scan mode. In one-time scan mode, ADSST is cleared by
hardware when the last selected analog input channel has been converted. As long as
ADSST = 1, new start commands to the ADC-block are ignored. An analog-to-digital
conversion in progress is aborted if ADSST is cleared by software.
ADCSA =1 results in a continuous scan of the selected analog inputs after a start of an
analog-to-digital conversion. ADCSA = 0 results in an one-time scan of the selected
analog inputs after a start of an analog-to-digital conversion.
If ADSRE = 1, then a rising edge at input ADEXS will start the analog-to-digital
conversion and generate a capture signal. If ADSRE = 0, then a rising edge at input
ADEXS has no effect.
If ADSFE = 1, then a falling edge at input ADEXS will start the analog-to-digital
conversion and generate a capture signal. If ADSFE = 0, then a falling edge at input
ADEXS has no effect.
2
ADCSA
1
ADSRE
0
ADSFE
ADPR1
ADPR0
PRESCALER DIVISOR (m)
0
0
1
1
0
1
0
1
2 (default by reset)
4
6
8
7
6
5
4
3
2
1
0
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
BIT
SYMBOL
DESCRIPTION
7 to 0
P5.7 to P5.0
Binary value of the logic level at input pins P5.0/ADC0 to P5.7/ADC.7.
BIT
SYMBOL
DESCRIPTION
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