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參數(shù)資料
| 型號(hào)： | P87C591VFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 27 PF 5% 50V NPO/COG (0805) CHIP CAP TR |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 86/161頁(yè) |
| 文件大?。?/td> | 588K |
| 代理商： | P87C591VFB |
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1999 Aug 19
86
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2.13 T
HE
S
TATUS
R
EGISTER
, S1STA
S1STA is an 8-bit read-only special function register. The
three least significant bits are always zero. The five most
significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no
relevant state information is available and no serial
interrupt is requested. All other S1STA values correspond
to defined SIO1 states. When each of these states is
entered, a serial interrupt is requested (SI = “1”). A valid
status code is present in S1STA one machine cycle after
SI is set by hardware and is still present one machine cycle
after SI has been reset by software.
Table 57
Serial clock rate
Note
1.
These frequencies exceed the upper limit of 100 kHz of the I
2
C-bus specification and cannot be used in an I
2
C-bus
application.
CR2
CR1
CR0
BIT FREQUENCY (kHz) at f
CLK
6 MHz
12 MHz
f
CLK
DIVIDED BY
16 MHz
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
23
27
31
37
6.25
50
100
47
54
63
75
12.5
100
200
62.5
71
83.3
100
17
133
(1)
267
(1)
0.65 < 55.6
0 < 253
256
224
192
160
960
120
60
1
1
1
0.24 > 62.5
0 < 255
0.49 < 62.5
0 < 254
96 x (256 (reload value Timer 1))
Reload value Timer 1 in Mode 2.
15.2.14 M
ORE
I
NFORMATION ON
SIO1 O
PERATING
M
ODES
The four operating modes are:
Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter
Data transfers in each mode of operation are shown in
Figures 37 to 40. These figures contain the following
abbreviations:
Abbreviation Explanation
S
Start condition
SLA
7-bit slave address
R
Read bit (high level at SDA)
W
Write bit (low level at SDA)
A
Acknowledge bit (low level at SDA)
A
Not acknowledge bit (high level at SDA)
Data
8-bit data byte
P
Stop condition
In Figures 37 to 40, circles are used to indicate when the
serial interrupt flag is set. The numbers in the circles show
the status code held in the S1STA register. At these points,
a service routine must be executed to continue or
complete the serial transfer. These service routines are
not critical since the serial transfer is suspended until the
serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code
in S1STA is used to branch to the appropriate service
routine. For each status code, the required software action
and details of the following serial transfer are given in
Tables 61 to 65.
15.2.14.1 Master Transmitter Mode:
In the master transmitter mode, a number of data bytes are
transmitted to a slave receiver (see Figure 37). Before the
master transmitter mode can be entered, S1CON must be
initialized as in Table 58.
CR0, CR1, and CR2 define the serial bit rate. ENS1 must
be set to logic 1 to enable SIO1. If the AA bit is reset, SIO1
will not acknowledge its own slave address or the general
call address in the event of another device becoming
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