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參數(shù)資料
| 型號(hào)： | P87C591VFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 27 PF 5% 50V NPO/COG (0805) CHIP CAP TR |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 33/161頁(yè) |
| 文件大?。?/td> | 588K |
| 代理商： | P87C591VFB |
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1999 Aug 19
33
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Notes
1.
2.
On Bus-Off the Error Warning Interrupt is set, if enabled.
If the Reset Mode was entered due to a Bus-off condition, the Receive Error Counter is cleared and the Transmit Error
Counter is initialized to 127 to count-down the CAN-defined Bus-off recovery time consisting of 128 occurrences of
11 consecutive recessive bits.
Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB would
show undefined data values (parts of old messages). If a message is transmitted, this message is written in parallel to
the Receive Buffer. A Receive Interrupt is generated only, if this transmission was forced by the Self Reception Request.
So, even if the Receive Buffer is empty, the last transmitted message may be read from the Receive Buffer until it is
overridden by the next received or transmitted message. Upon a Hardware Reset, the RXFIFO pointers are reset to the
physical RAM address “0”. Setting CR.0 by software or due to the Bus-Off event will reset the RXFIFO pointers to the
currently valid FIFO Start Address (RBSA Register) which is different from the RAM address ”0” after the first Release
Receive Buffer command.
3.
9
Rx Message Counter
RMC
Rx Message Counter
0
0
10
Rx Buffer Start Address
RBSA
Rx Buffer Start Address
00000000
b
0
X no change
11
Arbitr. Lost Capture
ALC
Arbitration Lost Capture
X no change
12
Error Code Capture
ECC
Error Code Capture
0
X no change
13
Error Warning Limit
EWLR
Error Warning Limit Register
96d
X no change
14
Rx Error Counter
RXERR
Receive Error Counter
0 (reset)
X no change
(2)
15
Tx Error Counter
TXERR
Transmit Error Counter
0 (reset)
X no change
(2)
29
ACF Mode
ACFMOD.7
ACFMOD.6
ACFMOD.5
ACFMOD.4
ACFMOD.3
ACFMOD.2
ACFMOD.1
ACFMOD.0
MFORMATB4
AMODEB4
MFORMATB3
AMODEB3
MFORMATB2
AMODEB2
MFORMATB1
AMODEB1
Message Format Bank4
Accept. Filt. Mode Bank Message
Format Bank3
Accept. Filt. Mode Bank3
Message Format Bank2
Accept. Filt. Mode Bank2
Message Format Bank1
Accept. Filt. Mode Bank1
0 (SFF)
0 (dual)
0 (SFF)
0 (dual)
0 (SFF)
0 (dual)
0 (SFF)
0 (dual)
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
30
ACF Enable
ACFEN.7
ACFEN.6
ACFEN.5
ACFEN.4
ACFEN.3
ACFEN.2
ACFEN.1
ACFEN.0
B4F2EN
B4F1EN
B3F2EN
B3F1EN
B2F2EN
B2F1EN
B1F2EN
B1F1EN
Bank 4 Filter 2 Enable
Bank 4 Filter 1 Enable
Bank 3 Filter 2 Enable
Bank 3 Filter 1 Enable
Bank 2 Filter 2 Enable
Bank 2 Filter 1 Enable
Bank 1 Filter 2 Enable
Bank 1 Filter 1 Enable
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
31
ACF Priority
ACFPRIO.7
ACFPRIO.6
ACFPRIO.5
ACFPRIO.4
ACFPRIO.3
ACFPRIO.2
ACFPRIO.1
ACFPRIO.0
B4F2PRIO
B4F1PRIO
B3F2PRIO
B3F1PRIO
B2F2PRIO
B2F1PRIO
B1F2PRIO
B1F1PRIO
Bank 4 Filter 2 Priority
Bank 4 Filter 1 Priority
Bank 3 Filter 2 Priority
Bank 3 Filter 1 Priority
Bank 2 Filter 2 Priority
Bank 2 Filter 1 Priority
Bank 1 Filter 2 Priority
Bank 1 Filter 1 Priority
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
32 to 35
Bank 1
ACR 0 to 3
ACR0 to ACR3
Acceptance Code Register
X no change
X no change
36 to 39
AMR 0 to 3
AMR0 to AMR3
Acceptance Mask Register
X no change
X no change
40 to 43
Bank 2
ACR 0 to 3
ACR0 to ACR3
Acceptance Code Register
X no change
X no change
44 to 47
AMR 0 to 3
AMR0 to AMR3
Acceptance Mask Register
X no change
X no change
48 to 51
Bank 3
ACR 0 to 3
ACR0 to ACR3
Acceptance Code Register
X no change
X no change
52 to 55
AMR 0 to 3
AMR0 to AMR3
Acceptance Mask Register
X no change
X no change
56 to 59
Bank 4
ACR 0 to 3
ACR0 to ACR3
Acceptance Code Register
X no change
X no change
60 to 63
AMR 0 to 3
AMR0 to AMR3
Acceptance Mask Register
X no change
X no change
96 to 108
Rx Buffer
RXB
Receive Buffer
X empty
(3)
X empty
(3)
112 to 124
Tx Buffer
TXB
Transmit Buffer
X no change
X no change
125 to 127
General Purpose RAM
General Purpose RAM
X no change
X no change
ADDR.
REGISTER
BIT
SYMBOL
NAME
RESET BY
HARDWARE
SETTING MOD.0 BY
SOFTWARE OR
DUE TO BUS-OFF
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