參數(shù)資料
型號(hào)： P87C554SFBD
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 X 1.40 MM, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 38/76頁(yè)
文件大?。?/td> 400K
代理商： P87C554SFBD
Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2000 Nov 10
38
If the STA and STO bits are both set, the a STOP condition is
transmitted to the I
2
C bus if SIO1 is in a master mode (in a slave
mode, SIO1 generates an internal STOP condition which is not
transmitted). SIO1 then transmits a START condition.
STO = “0”: When the STO bit is reset, no STOP condition will be
generated.
SI
,
THE
S
ERIAL
I
NTERRUPT
F
LAG
SI = “1”: When the SI flag is set, then, if the EA and ES1 (interrupt
enable register) bits are also set, a serial interrupt is requested. SI is
set by hardware when one of 25 of the 26 possible SIO1 states is
entered. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available.
While SI is set, the low period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A high level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = “0”: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
AA
,
THE
A
SSERT
A
CKNOWLEDGE
F
LAG
AA = “1”: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line
when:
– The “own slave address” has been received
– The general call address has been received while the general call
bit (GC) in S1ADR is set
– A data byte has been received while SIO1 is in the master
receiver mode
– A data byte has been received while SIO1 is in the addressed
slave receiver mode
AA = “0”: if the AA flag is reset, a not acknowledge (high level to
SDA) will be returned during the acknowledge clock pulse on SCL
when:
– A data has been received while SIO1 is in the master receiver
mode
– A data byte has been received while SIO1 is in the addressed
slave receiver mode
When SIO1 is in the addressed slave transmitter mode, state C8H
will be entered after the last serial is transmitted (see Figure 43).
When SI is cleared, SIO1 leaves state C8H, enters the not
addressed slave receiver mode, and the SDA line remains at a high
level. In state C8H, the AA flag can be set again for future address
recognition.
When SIO1 is in the not addressed slave mode, its own slave
address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, SIO1 can be temporarily released from the I
2
C bus while the
bus status is monitored. While SIO1 is released from the bus,
START and STOP conditions are detected, and serial data is shifted
in. Address recognition can be resumed at any time by setting the
AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will
be recognized at the end of the byte transmission.
CR
0,
CR
1,
AND
CR
2,
THE
C
LOCK
R
ATE
B
ITS
These three bits determine the serial clock frequency when SIO1 is
in a master mode. The various serial rates are shown in Table 5.
A 12.5 kHz bit rate may be used by devices that interface to the I
2
C
bus via standard I/O port lines which are software driven and slow.
100 kHz is usually the maximum bit rate and can be derived from a
8 MHz, 6 MHz, or a 3 MHz oscillator. A variable bit rate (0.24 kHz to
62.5 kHz) may also be used if Timer 1 is not required for any other
purpose while SIO1 is in a master mode.
The frequencies shown in Table 5 are unimportant when SIO1 is in a
slave mode. In the slave modes, SIO1 will automatically synchronize
with any clock frequency up to 100 kHz.
The Status Register, S1STA:
S1STA is an 8-bit read-only special
function register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined SIO1 states. When each of
these states is entered, a serial interrupt is requested (SI = “1”). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
Table 5.
Serial Clock Rates
BIT FREQUENCY (kHz) AT f
OSC
6 MHz
8 MHz
CR2
CR1
CR0
3 MHz
12 MHz
2
15 MHz
2
117
1
134
1
156
1
188
1
31
250
1
500
1
1.22 < 52.1
0 < 250
f
OSC
DIVIDED BY
128
112
96
80
48
60
30
48
×
(256 – (reload value Timer 1))
Reload value Timer 1 in Mode 2.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
23
27
31
37
6.25
50
100
47
54
63
75
12.5
100
200
62.5
71
83.3
100
17
133
1
267
1
94
107
1
125
1
150
1
25
200
1
400
1
0.24 < 62.5
0 < 255
0.49 < 62.5
0 < 254
0.65 < 55.6
0 < 253
0.98 < 50.0
0 < 251
NOTES:
1. These frequencies exceed the upper limit of 100 kHz of the I
2
C-bus specification and cannot be used in an I
2
C-bus application.
2. At f
OSC
= 12 MHz/15 MHz the maximum I
2
C bus rate of 100 kHz cannot be realized due to the fixed divider rates.
相關(guān)PDF資料
PDF描述
P83C554SFBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P87C554 80C51 8-bit microcontroller(80C51 8位微控制器)
P87C654X2 Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125
P83C654X2 80C51 8-bit microcontroller family 16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P83C654EFP CONN HEADER 11POS SGL PCB 30GOLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P87C557E8 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8 BIT MICROCONTROLLER
P87C557E8EFB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
P87C557E8EFB/01,55 功能描述:8位微控制器 -MCU 8B MICROCONTROLLER RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P87C557E8EFB/01,557 制造商:NXP Semiconductors 功能描述:
P87C575EBA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*