參數(shù)資料
型號： P87C554SFBD
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 X 1.40 MM, PLASTIC, LQFP-64
文件頁數(shù)： 30/76頁
文件大小： 400K
代理商： P87C554SFBD
Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2000 Nov 10
30
ECT0
BIT
SYMBOL
FUNCTION
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
Enable Timer T2 overflow interrupt(s)
Enable T2 Comparator 2 interrupt
Enable T2 Comparator 1 interrupt
Enable T2 Comparator 0 interrupt
Enable T2 Capture register 3 interrupt
Enable T2 Capture register 2 interrupt
Enable T2 Capture register 1 interrupt
Enable T2 Capture register 0 interrupt
SU00755
ECT1
ECT2
ECT3
ECM0
ECM1
ECM2
ET2
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IEN1 (E8H)
In all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled.
Figure 28. Interrupt Enable Register (IEN1)
PX0
BIT
SYMBOL
FUNCTION
IP0.7
IP0.6
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
–
PAD
PS1
PS0
PT1
PX1
PT0
PX0
Unused
ADC interrupt priority level
SIO1 (I
2
C) interrupt priority level
SIO0 (UART) interrupt priority level
Timer 1 interrupt priority level
External interrupt 1 priority level
Timer 0 interrupt priority level
External interrupt 0 priority level
SU00763
PT0
PX1
PT1
PS0
PS1
PAD
–
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IP0 (B8H)
Figure 29. Interrupt Priority Register (IP0)
PX0H
BIT
SYMBOL
FUNCTION
IP0H.7
IP0H.6
IP0H.5
IP0H.4
IP0H.3
IP0H.2
IP0H.1
IP0H.0
–
PADH
PS1H
PS0H
PT1H
PX1H
PT0H
PX0H
Unused
ADC interrupt priority level high
SIO1 (I
2
C) interrupt priority level high
SIO0 (UART) interrupt priority level high
Timer 1 interrupt priority level high
External interrupt 1 priority level high
Timer 0 interrupt priority level high
External interrupt 0 priority level high
SU00983
PT0H
PX1H
PT1H
PS0H
PS1H
PADH
–
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IP0H (B7H)
Figure 30. Interrupt Priority Register High (IP0H)
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