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| 型號： | P83CE560EFB |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | NPN Silicon Power Transistor, TO-220F-3SL |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 54/84頁 |
| 文件大?。?/td> | 441K |
| 代理商： | P83CE560EFB |
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1997 Aug 01
54
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
19 INSTRUCTION SET
The P8xCE560 uses the powerful instruction set of the
PCB80C51. It consists of 49 single byte, 45 two byte and
17 three byte instructions. Using a 16 MHz crystal, 64 of
the instructions are executed in 0.75
μ
s, 45 in 1,5
μ
s and
the multiply, divide instructions in 3
μ
s.
A summary of the instruction set is given in
Tables 76, 77, 78, 79 and 80.
The P8xCE560 has additional Special Function Registers
to control the on-chip peripherals.
19.1
Addressing modes
Most instructions have a ‘destination, source’ field that
specifies the data type, addressing modes and operands
involved. For all these instructions, except for MOVs, the
destination operand is also the source operand
(e.g. ADD A,R7).
There are five kinds of addressing modes:
Register Addressing
– R0 to R7 (4 banks)
– A,B,C (bit), AB (2 bytes), DPTR (double byte)
Direct Addressing
– lower 128 bytes of internal main RAM (including the
four R0 to R7 register banks)
– Special Function Registers
– 128 bits in a subset of the internal main RAM
– 128 bits in a subset of the Special Function Registers
Register-Indirect Addressing
– internal main RAM (@R0, @R1, @SP [PUSH/POP])
– internal auxiliary RAM (@R0, @R1, @DPTR)
– external Data Memory (@R0, @R1, @DPTR)
Immediate Addressing
– Program Memory (in-code 8 bit or 16 bit constant)
Base-Register-plus-Index-Register-Indirect Addressing
– Program Memory look-up table
(@DPTR+A, @PC+A).
The first three addressing modes are usable for
destination operands.
19.2
80C51 family instruction set
Table 75
Instructions that affect flag settings; note 1
Note
1.
Note that operations on SFR byte address 208 or bit
addresses 209 to 215 (i.e. the PSW or bits in the
PSW) will also affect flag settings.
X = don’t care.
2.
INSTRUCTION
FLAG
(2)
C
OV
AC
ADD
ADDC
SUBB
MUL
DIV
DA
RRC
RLC
SETB C
CLR C
CPL C
ANL C, bit
ANL C,/bit
ORL C, bit
ORL C,/bit
MOV C, bit
CJNE
X
X
X
0
0
X
X
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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