參數(shù)資料
型號(hào)： P83CE560EFB
廠(chǎng)商： NXP Semiconductors N.V.
英文描述： NPN Silicon Power Transistor, TO-220F-3SL
中文描述： 8位微控制器
文件頁(yè)數(shù)： 34/84頁(yè)
文件大小： 441K
代理商： P83CE560EFB
1997 Aug 01
34
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
13.2
Serial I/O Port: SIO1 (I
2
C-bus interface)
The SIO1 of the P8xCE560 provides the fast mode, which
allows a fourth-fold increase of the bit rate up to 400 kHz.
Nevertheless it is downward compatible, i.e. it can be used
in a 0 to 100 kbit/s I
2
C-bus system.
Except from the bit rate selection (see Table 48) and the
timing of the SCL and SDA signals (see Chapter 11) the
SIO circuit is the same as described in detail in the
80C51-based “Data Handbook IC20”for the 8xC552
microcontroller.
The I
2
C-bus is a simple bidirectional 2-wire bus for efficient
inter-IC data exchange. Features of the I
2
C-bus are:
Only two bus lines are required: a serial clock line (SCL)
and a serial data line (SDA)
Each device connected to the bus is software
addressable by a unique address
Masters can operate as master transmitter or as master
receiver
It is a true multi-master bus including collision detection
and arbitration to prevent data corruption if two or more
masters simultaneously initiate data transfer
Serial clock synchronization allows devices with
different bit rates to communicate via the same serial
bus
ICs can be added to or removed from an I
2
C-bus system
without affecting any other circuit on the bus
Fault diagnostics and debugging are simple;
malfunctions can be immediately traced.
For more information on the I
2
C-bus specification
(including fast-mode) please refer to the Philips publication
“The I
2
C-bus and how to use it”ordering number
9398 393 40011 and/or the 80C51-based
“Data Handbook IC20”
The on-chip I
2
C logic provides a serial interface that meets
the I
2
C-bus specification, supporting 4 modes of operation:
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
The SIO1 logic performs a byte oriented data transport;
clock generation, address recognition and bus control
arbitration are all controlled by hardware. Via two pins the
external I
2
C-bus is interfaced to the SIO1 logic: SCL serial
clock I/O and SDA serial data I/O (SFR S1CON bit ENS1
for enabling the SIO1 logic).
The SIO1 logic handles byte transfer autonomously.
It keeps track of the serial transfers, and a status register
(S1STA) reflects the status of SIO1 and the I
2
C-bus.
Via 4 SFRs the CPU interfaces to the I
2
C-bus logic:
S1CON; Serial Control Register. Bit-addressable by the
CPU
S1STA; Status Register whose contents may be used
as a vector to service routines
S1DAT; Data Shift Register. The data byte is stable as
long as SI = 1 (SFR S1CON)
S1ADR; Slave Address Register. Its LSB
enables/disables general call address recognition.
13.2.1
S
ERIAL
C
ONTROL
R
EGISTER
(S1CON)
The CPU can read from and write to this 8-bit, directly
addressable SFR. Two bits are affected by the SIO1
hardware:
the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present
on the I
2
C-bus. The STO bit is also cleared when
ENS1 = 0.
When SIO1 is in a master mode, serial clock frequency is
determined by the clock rate bits CR2, CR1 and CR0.
The various bit rates are shown in Table 48.
The data shown in Table 48 do not apply to SIO1 in a slave
mode. In the slave modes, SIO1 will automatically
synchronize with any clock frequency up to 400 kHz.
However, serial clock frequencies above 100 kHz require
an oscillator frequency f
clk
of at least 12 MHz.
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