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參數(shù)資料
| 型號(hào)： | P83C554SFBD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 35/76頁 |
| 文件大?。?/td> | 400K |
| 代理商： | P83C554SFBD |
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Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2000 Nov 10
35
A
RBITRATION
AND
S
YNCHRONIZATION
L
OGIC
In the master transmitter mode, the arbitration logic checks that
every transmitted logic 1 actually appears as a logic 1 on the I
2
C
bus. If another device on the bus overrules a logic 1 and pulls the
SDA line low, arbitration is lost, and SIO1 immediately changes from
master transmitter to slave receiver. SIO1 will continue to output
clock pulses (on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the master receiver mode. Loss of
arbitration in this mode can only occur while SIO1 is returning a “not
acknowledge: (logic 1) to the bus. Arbitration is lost when another
device on the bus pulls this signal LOW. Since this can occur only at
the end of a serial byte, SIO1 generates no further clock pulses.
Figure 36 shows the arbitration procedure.
The synchronization logic will synchronize the serial clock generator
with the clock pulses on the SCL line from another device. If two or
more master devices generate clock pulses, the “mark” duration is
determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the
longest “spaces.” Figure 37 shows the synchronization procedure.
A slave may stretch the space duration to slow down the bus
master. The space duration may also be stretched for handshaking
purposes. This can be done after each bit or after a complete byte
transfer. SIO1 will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been
transferred. The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
ACK
1. Another device transmits identical serial data.
SDA
1
2
3
4
8
9
SCL
(1)
(1)
(2)
(3)
2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is
lost, and SIO1 enters the slave receiver mode.
3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will
not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.
SU00967
Figure 36. Arbitration Procedure
(1)
SCL
(3)
(1)
SDA
MARK
DURATION
SPACE DURATION
(2)
1. Another service pulls the SCL line low before the SIO1 “mark” duration is complete. The serial clock generator is immediately
reset and commences with the “space” duration by pulling SCL low.
2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state
until the SCL line is released.
3. The SCL line is released, and the serial clock generator commences with the mark duration.
SU00968
Figure 37. Serial Clock Synchronization
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| P83C557E4 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller |
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| P83C557E4EFB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller |
| P83C557E4EFB/YYY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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