參數(shù)資料
型號(hào)： P83C524EFB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： CONN 2O POS BOT ENTRY SFMT (BULK) 4-534991-2 TYCO, FCI BERG 69154-310
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 X 1.75 MM, PLASTIC, QFP-44
文件頁數(shù)： 54/76頁
文件大?。?/td> 400K
代理商： P83C524EFB
1997 Dec 15
54
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Notes to the DC characteristics
1.
Conditions for:
a) The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5 ns;
V
IL
= V
SS
+0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V
DD
;
the WDT is disabled (by the external RESET).
2.
Conditions for:
a) The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5 ns;
V
IL
= V
SS
+0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected; the WDT is disabled; EA = RST = V
SS
;
Port 0 = P1.6 = P1.7 = V
DD
.
3.
Conditions for:
a) The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
WDT is disabled; EA = RST = XTAL1 = V
SS
; Port 0 = P1.6 = P1.7 = V
DD
.
4.
Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level
output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0
and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases
(capacitive loading
>
100pF), the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
5.
Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily
fall below the 0.9 V
DD
specification when the address bits are stabilizing.
6.
The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so a voltage below 0.3 V
DD
will be
recognized as a logic 0 while an input above 0.7 V
DD
will be recognized as a logic 1.
7.
Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
a) Maximum I
OL
per port pin:10 mA.
b) Maximum I
OL
per 8-bit port:- Port 0: 26 mA; Ports 1, 2 and 3: 15 mA.
c) Maximum total I
OL
for all output pins: 71 mA. If I
OL
exceeds the test condition,
V
OL
may exceed the related specification.
d) Pins are not guaranteed to sink current greater than the listed test conditions.
8.
I
DD
max. at other frequencies can be derived from Fig.26 where f is the external oscillator frequency in MHz;
I
DD
max. is given in mA.
V
OH1
HIGH level output voltage
Port0in in external bus mode,
ALE, PSEN, RST
I
OH
=
800
μ
A;
V
DD
= 5 V
±
10%
I
OH
=
300
μ
A;
I
OH
=
80
μ
A; note 5
2.4
0.75V
DD
0.9V
DD
V
R
RST
C
I/O
RST pull
down resistor
I/O pin capacitance
50
150
10
k
pF
test frequency = 1 MHz;
T
amb
= 25
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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