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參數(shù)資料
| 型號： | P83C524EFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CONN 2O POS BOT ENTRY SFMT (BULK) 4-534991-2 TYCO, FCI BERG 69154-310 |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 32/76頁 |
| 文件大小： | 400K |
| 代理商： | P83C524EFB |
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1997 Dec 15
32
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
13 BIT-LEVEL I
2
C INTERFACE
This bit-level serial I/O interface supports the I
2
C-bus (see
Fig.18). P1.6/SCL and P1.7/SDA are the serial I/O pins.
These two pins meet the I
2
C specification concerning the
input levels and output drive capability. Consequently,
these pins have an open drain output configuration. All
four modes of the I
2
C-bus are supported:
master transmitter
master receiver
slave transmitter
slave receiver.
The advantages of the bit-level I
2
C hardware compared
with a full software I
2
C implementation are:
the hardware can generate the SCL pulse
testing a single bit (RBF respectively, WBF) is sufficient
as a check for error free transmission.
The bit-level I
2
C hardware operates on serial bit level and
performs the following functions:
filtering the incoming serial data and clock signals
recognizing the START condition
generating a serial interrupt request SI after reception of
a START condition and the first falling edge of the serial
clock
recognizing the STOP condition
recognizing a serial clock pulse on the SCL line
latching a serial bit on the SDA line (SDI)
stretching the SCL LOW period of the serial clock to
suspend the transfer of the next serial data bit
setting Read Bit Finished (RBF) when the SCL clock
pulse has finished and Write Bit Finished (WBF) if there
is no arbitration loss detected (i.e. SDA = 0 while
SDO = 1)
setting a serial clock LOW-to-HIGH detected (CLH) flag
setting a Bus Busy (BB) flag on a START condition and
clearing this flag on a STOP condition
releasing the SCL line and clearing the CLH, RBF and
WBF flags to resume transfer of the next serial data bit
generating an automatic clock if the single bit data
register S1BIT is used in master mode.
The following functions must be done in software:
handling the I
2
C START interrupts
converting serial to parallel data when receiving
converting parallel to serial data when transmitting
comparing the received slave address with its own
interpreting the acknowledge information
guarding the I
2
C status if RBF or WBF = 0.
additionally, if acting as master:
generating START and STOP conditions
handling bus arbitration
generating serial clock pulses if S1BIT is not used.
Three SFRs control the bit-level I
2
C interface: S1INT,
S1BIT and S1SCS.
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| P83C524EFP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers |
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