參數(shù)資料
型號: P83C524EFB
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: CONN 2O POS BOT ENTRY SFMT (BULK) 4-534991-2 TYCO, FCI BERG 69154-310
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 X 1.75 MM, PLASTIC, QFP-44
文件頁數(shù): 35/76頁
文件大?。?/td> 400K
代理商: P83C524EFB
1997 Dec 15
35
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
13.2.1
R
EADING OR
W
RITING THE
S1BIT SFR
Reading or writing the S1BIT SFR starts an I
2
C bit I/O
sequence: some flags are cleared (SI, CLH, RBF, WBF),
clock stretching is finished and the auto-clock is started.
An auto-clock pulse is 'OR-ed' with SCO and thus will be
output only if the SCO flag has been set to 0. SCO = 1
inhibits the auto-clock start, so a dummy read or write of
S1BIT SFR can be used to finish clock stretching and clear
SI, CLH, RBF and WBF if the auto-clock is not used.
The auto-clock is an active HIGH SCL pulse that starts 28
XTAL clock periods after the SDI read or SDO write via
S1BIT. The duration of the auto-clock pulse is 100 XTAL
clock periods. If the SCL line is kept LOW by any device
that wants to hold up the bus transfer, the auto-clock
counter waits after 20 XTAL clock periods so that the
auto-clock pulse length will be at least 80 XTAL clock
periods (5
μ
s at f
OSC
= 16 MHz).
Every bit I/O should be followed by a RBF or WBF bit test.
A bit transfer has been finished successfully if after reading
a bit the RBF flag is 1 or after writing a bit the WBF flag is
1. When after reading a bit the RBF flag is still 0, the bus
status just before the S1SCS status read can be
determined as follows:
if CLH = 0 then a bus device is still stretching the clock
if SCI = 1 while CLH = 1 then the SCL pulse is not
finished
if BB = 0 there has been a STOP condition.
When after writing a bit the WBF flag is still 0 and none of
the 3 status conditions mentioned for RBF are found then
a 'bus arbitration lost' condition will be the cause. This can
be determined also from the states of the received bit and
the last transmitted bit: 'arbitration loss' if SDO = 1 and
SDI = 0.
13.3
Control and Status Register for the I
2
C-bus (S1SCS)
Table 19
Control and Status register for the I
2
C-bus (address D8H)
Notes
1.
SDI and SCI bits
: read-modify-write operations like 'SETB bit' or 'CLR bit' access SDO and SCO for reading and
writing.
CLH bit
: writing a logic 0 clears this bit, writing a 1 has no effect.
RBF and WBF bits
: writing a logic 0 to CLH also clears these bits.
X = don't care.
2.
3.
4.
7
6
5
4
3
2
1
0
READ
SDI
(1)
SCI
(1)
CLH
(2)
BB
RBF
(3)
WBF
(4)
STR
ENS
WRITE
SDO
SCO
CLH
(2)
X
X
X
STR
ENS
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