參數(shù)資料
型號： P80CE560
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 8/84頁
文件大?。?/td> 441K
代理商： P80CE560
1997 Aug 01
8
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
6.2
Pin description
Table 1
To avoid a ‘latch-up’ effect at power-on: V
SS
0.5 V < ‘voltage at any pin at any time’ < V
DD
+ 0.5 V.
Pin description for QFP80 (SOT318-2)
SYMBOL
PIN
DESCRIPTION
V
ref(n)(A)
V
ref(p)(A)
V
SSA1
V
DDA1
P5.7/ADC7 to
P5.0/ADC0
V
SS1
to V
SS4
1
2
3
4
5 to 12
Low-end of ADC
reference resistor.
High-end of ADC
reference resistor.
Ground
, analog part. For ADC receiver and reference voltage.
Power supply
, analog part (+5 V). For ADC receiver and reference voltage.
Port 5 (P5.7 to P5.0)
: 8-bit input port lines;
ADC7 to ADC0
: 8 input channels to the ADC.
Ground;
digital part; circuit ground potential. V
SS1
, V
SS2
, V
SS4
must be connected,
V
SS3
is internally connected to digital ground, but should be connected externally.
Power supply,
digital part (+5 V). Power supply pins during normal operation and
power reduction modes. All pins must be connected.
Start ADC operation.
Input starting ADC, triggered by a programmable edge; ADC
operation can also be started by software. This pin must not float.
Pulse Width Modulation output 0.
Pulse Width Modulation output 1.
Enable Watchdog Timer (WDT):
enable for T3 Watchdog Timer and disable
Power-down mode. This pin must not float.
Port 4
(
P4.0 to P4.7)
: 8-bit quasi-bidirectional I/O port lines;
CMSR0 to CMSR5
: compare and set/reset outputs for Timer T2;
CMT0 to CMT1
: compare and toggle outputs for Timer T2.
13, 29,
54, 67
14, 28,
53, 66
15
V
DD1
to V
DD4
ADEXS
PWM0
PWM1
EW
16
17
18
P4.0/CMSR0 to
P4.5/CMSR5
P4.6/CMT0 to
P4.7/CMT1
RSTOUT
19 to 22,
24, 25
26, 27
23
Reset output
of the P8xCE560 for resetting peripheral devices during initialization
and Watchdog Timer overflow.
Reset input
to reset the P8xCE560.
Port 1 (P1.0 to P1.7)
: 8-bit quasi-bidirectional I/O port lines;
CT0I to CT3I
: Capture timer inputs for Timer T2;
INT2 to INT5
: external interrupts 2 to 5;
T2
: T2 event input (rising edge triggered);
RT2
: T2 timer reset input (rising edge triggered).
RSTIN
P1.0/CT0I/INT2 to
P1.3/CT3I/INT5
P1.4/T2 to
P1.5/RT2
P1.6 to P1.7
SCL
SDA
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
n.c.
30
31 to 34
35, 36
37 to 38
39
40
41
42
43
44
45
46
47
48
49, 50
I
2
C-bus serial clock I/O port.
If SCL is not used, it must be connected to V
SS
.
I
2
C-bus serial data I/O port.
If SDA is not used, it must be connected to V
SS
.
Port 3 (P3.0 to P3.7)
: 8-bit quasi-bidirectional I/O port lines;
RXD
: Serial input port;
TXD
: Serial output port;
INT0
: External interrupt input 0;
INT1
: External interrupt input 1;
T0
: Timer 0 external interrupt input;
T1
: Timer 1external interrupt input;
WR
: External Data Memory Write strobe;
RD
: External Data Memory Read strobe.
Not connected pins.
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