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參數(shù)資料
| 型號： | P80CE560 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 21/84頁 |
| 文件大?。?/td> | 441K |
| 代理商： | P80CE560 |
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1997 Aug 01
21
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
In continuous scan mode (ADCSA = 1; ADCON.2) the
ADC start and status flag ADSST (ADCON.3) retains the
set state and the autoscan loop restarts from the
beginning. In one-time scan mode (ADCSA = 0)
conversions stop after the last selected analog input was
converted, ADINT (ADCON.4) is set and ADSST is
cleared automatically.
ADSST cannot be set (neither externally nor by software)
as long as ADINT = 1, i.e. as long as ADINT is set, a new
conversion start - by setting flag ADSST - is inhibited;
actually it is only delayed until ADINT is cleared. If a logic 1
is written to ADSST while ADINT = 1, this new value is
internally latched and preserved, not setting ADSST until
ADINT = 0. In this state, a read of SFR ADCON will display
ADSST = 0, because always the effective ADC status is
read.
Note that under software control the analog inputs can also
be converted in arbitrary order, when one-time scan mode
is selected and in SFR ADPSS only one bit is set at a time.
In this case ADINT is set and ADSST is cleared after every
conversion.
11.5
ADC during Idle and Power-down mode
The analog-to-digital converter is active only when the
microcontroller is in normal operating mode. If the Idle or
Power-down mode is activated, then the ADC is switched
off and put into a power saving idle state - a conversion in
progress is aborted, a previously set ADSST flag is cleared
and the internal clock is halted. The conversion result
registers are not affected.
The interrupt flag ADINT will not be set by activation of Idle
or Power-down mode. A previously set flag ADINT will not
be cleared by the hardware. (Note: ADINT cannot be
cleared by hardware at all, except for a reset - it must be
cleared by the user software.)
After a wake-up from Idle or Power-down mode a set flag
ADINT indicates that at least one autoscan loop was
finished completely before the microcontroller was put into
the respective power reduction mode and it indicates that
the stored result data may be fetched now - if desired.
For further information on Idle and Power-down modes,
refer to Chapter 15.
11.6
ADC resolution and characteristics
The ADC system has its own analog supply pins V
DDA1
and V
SSA1
. It is referenced by two special reference
voltage input pins sourcing the resistance ladder of the
DAC: V
ref(p)(A)
and V
ref(n)(A)
. The voltage between V
ref(p)(A)
and V
ref(n)(A)
defines the full-scale range. Due to the 10-bit
resolution the full scale range is divided into 1024 unit
steps.
The unit step voltage is 1 LSB, which is typically 5 mV
(V
ref(p)(A)
= 5.12 V, V
ref(n)(A)
= 0 V = V
SSA1
).
The DAC's resistance ladder has 1023 equally spaced
taps, separated by a unit resistance ‘R’.
The first tap is located 0.5
×
R above V
ref(n)(A)
, the last tap
is located 1.5
×
R below V
ref(p)(A)
. This results in a total
ladder resistance of 1024
×
R. This structure ensures that
the DAC is monotonic and results in a symmetrical
quantization error. For input voltages between:
V
ref(n)(A)
and [V
ref(n)(A)
+
1
2
×
LSB] the 10-bit conversion
result code will be 0000000000B (= 000H or 0D)
[V
ref(p)(A)
3
2
×
LSB] and V
ref(p)(A)
the 10-bit conversion
result code will be 1111111111B (= 3FFH or 1023D).
The result code corresponding to an analog input voltage
(V
in(A)
) can be calculated from the formula:
The analog input voltage should be stable when it is
sampled for conversion. At any times the input voltage
slew rate must be less than 10 V/ms (5 V conversion
range) in order to prevent an undefined result.
This maximum input voltage slew rate can be ensured by
an RC low pass filter with R = 2.2 k
and C = 100 nF.
The capacitor between analog input pin and analog
ground pin shall be placed close to the pins in order to
have maximum effect in minimizing input noise coupling.
11.7
ADC after reset
After a reset of the microcontroller the ADCON and
ADPSS registers are initialized to zero. Registers ADRSLn
and ADRSH are not initialized by a reset.
Result code
1024
V
ref(p)(A)
V
ref(n)(A)
V
ref(n)(A)
–
–
V
×
=
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| P80CE598FFB/00,518 | 功能描述:8位微控制器 -MCU 8B MCU ON-CHIP CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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