參數(shù)資料
型號： P80C591
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller with CAN controller
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 119/161頁
文件大?。?/td> 588K
代理商： P80C591
1999 Aug 19
119
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
16.1.7
T
IMER
T2 I
NTERRUPT
F
LAG
R
EGISTER
TM2IR
Seven of the eight Timer T2 interrupt flags are located in
special function register TM2lR (see Section 16.1.7.1).
The eights flag is TM2CON.4.
The CT0l and CT1I flags are set during S4 of the cycle in
which the contents of Timer T2 are captured. CT0l is
scanned by the interrupt logic during S2, and CT1I is
scanned during S3. CT2l and CT3l are set during S6 and
are scanned during S4 and S5. The associated interrupt
requests are recognized during the following cycle. If these
flags are polled, a transition at CT0l or CT1I will be
recognized one cycle before a transition on CT2l or CT3l
since registers are read during S5. The CMI0, CMl1 and
CMl2 flags are set during S6 of the cycle following a match.
CMl0 is scanned by the interrupt logic during S2; CMl1 and
CMl2 are scanned during S3 and S4. A match of CMl0 and
CMl1 will be recognized by the interrupt logic (or by polling
the flags) two cycles after the match takes place. A match
of CMl2 will cause no interrupt, this flag can be polled only.
The 16-bit overflow flag (T2OV) and the byte overflow flag
(T2BO) are set during S6 of the cycle in which the overflow
occurs. These flags are recognized by the interrupt logic
during the next cycle. Special function register lP1 (see
Section 16.1.7.2) is used to determine the Timer T2
interrupt priority. Setting a bit high gives that function a
high priority, and setting a bit low gives the function a low
priority. The functions controlled by the various bits of the
lP1 register are shown in Section 16.1.6.2.
16.1.7.1
Interrupt Flag Register (TM2IR)
Table 78
Interrupt flag register (address C8H)
Table 79
Description of TM2IR bits
16.1.7.2
Interrupt Priority Register 1 (IP1)
Table 80
Interrupt Priority Register 1 (address F8H)
Table 81
Description of IP1 bits
7
6
5
4
3
2
1
0
T2OV
CMI2/CAN
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
BIT
7
6
5
4
3
2
1
0
SYMBOL
T2OV
CMI2/CAN
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
DESCRIPTION
T2: 16-bit overflow interrupt flag.
CM2: flag (for polling only). CAN: CAN interrupt flag (polling only).
CM1: interrupt flag.
CM0: interrupt flag.
CT3: interrupt flag.
CT2: interrupt flag.
CT1: interrupt flag.
CT0: interrupt flag.
7
6
5
4
3
2
1
0
PT2
PCAN
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
BIT
7
6
5
4
3
2
1
0
SYMBOL
PT2
PCAN
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
DESCRIPTION
T2 overflow interrupt(s) priority level.
CAN interrupt priority level.
T2 comparator 1 priority interrupt level.
T2 comparator 0 priority interrupt level.
T2 capture register 3 priority interrupt level.
T2 capture register 2 priority interrupt level.
T2 capture register 1 priority interrupt level.
T2 capture register 0 priority interrupt level.
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