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參數(shù)資料
| 型號： | P80C562EFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 8/52頁 |
| 文件大?。?/td> | 299K |
| 代理商： | P80C562EFA |
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1997 Apr 08
8
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
XTAL1
35
Crystal Oscillator Input:
input to the inverting amplifier that forms the oscillator, and
input to the internal clock generator. Receives the external oscillator clock signal when
an external oscillator is used.
Digital
ground pins.
Not connected.
P2.0 to P2.7:
8-bit quasi-bidirectional I/O port lines;
A08 to A15:
High-order address byte for external memory.
V
SS
n.c.
P2.0/A08
to
P2.7/A15
PSEN
36, 37
38
39 to 46
47
Program Store Enable:
read strobe to the external program memory via Port 0 and 2.
Is activated twice each machine cycle during fetches from external program memory.
When executing out of external program memory two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains HIGH)
during no fetches from external program memory. PSEN can sink/source 8 LSTTL
inputs and can drive CMOS inputs without external pull-ups.
Address Latch Enable:
latches the low byte of the address during access of external
memory in normal operation. It is activated every six oscillator periods except during an
external data memory access. ALE can sink/source 8 LSTTL inputs and can drive
CMOS inputs without an external pull-up. To prohibit the toggling of the ALE pin (RFI
noise reduction) the RFI bit in the Power Control Register must be set by software.
External Access:
if, during RESET, EA is HIGH the CPU executes out of the internal
program memory provided the program Counter is less than 8192. If, during RESET,
EA is LOW the CPU executes out of external program memory via Port 0 and Port 2.
EA is not allowed to float. EA is latched during RESET and don’t care after RESET.
P0.7 to P0.0:
8-bit open drain bidirectional I/O port lines;
AD7 to AD0:
Multiplexed Low-order address and Data bus for external memory.
ALE
48
EA
49
P0.7/AD7
to
P0.0/AD0
AV
REF-
AV
REF+
AV
SS
AV
DD
P5.7/ADC7
to
P5.0/ADC0
50 to 57
58
59
60
61
Low-end of ADC
(analog-to-digital conversion) reference resistor.
High-end of ADC
(analog-to-digital conversion) reference resistor.
Ground
, analog part. For ADC receiver and reference voltage.
Power supply
, analog part (+5 V). For ADC receiver and reference voltage.
P5.7 to P5.0:
8-bit input port lines;
ADC7 to ADC0:
eight analog ADC inputs
62 to 68,
1
SYMBOL
PIN
DESCRIPTION
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