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| 型號： | P80C562EFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 28/52頁 |
| 文件大?。?/td> | 299K |
| 代理商： | P80C562EFA |
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1997 Apr 08
28
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
15 REDUCED POWER MODES
15.1
Idle and Power-down operation
Idle mode operation permits the interrupt, serial ports and
timer blocks to continue to function while the CPU is
halted. The Idle and Power-down clock configuration is
shown in Fig.13. The following functions are switched off
when the processor enters the Idle mode.
Timer T2 - stopped and reset
PWM0 and PWM1 - reset, output HIGH
ADC - aborted if in progress.
The following functions remain active during Idle mode.
These functions may generate an interrupt or reset and
thus end the Idle mode.
Timer 0, Timer 1
Timer T3
SIO
External Interrupt.
The Power-down operation freezes the oscillator.
The Power-down mode can only be activated by setting
the PD bit in the PCON register. The PD bit can only be set
if the EW input is HIGH.
15.1.1
I
DLE MODE
The instruction that sets PCON.0 is the last instruction
executed in the normal operating mode before Idle mode
is activated. Once in the Idle mode, the CPU status is
preserved in its entirety: the Stack Pointer, Program
Counter, Program Status Word, Accumulator, RAM and all
other registers maintain their data during Idle mode.
The status of the external pins during Idle mode is shown
in Table 33.
There are two ways to terminate the Idle mode:
Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware terminating the Idle mode.
The interrupt is serviced, and following the return from
interrupt instruction RETI, the next instruction to be
executed will be the one which follows the instruction
that wrote a logic 1 to PCON.0. The flag bits GF0 and
GF1 may be used to determine whether the interrupt
was received during normal execution or during the Idle
mode. For example, the instruction that writes to
PCON.0 can also set or clear one or both flag bits. When
Idle mode is terminated by an interrupt, the service
routine can examine the status of the flag bits.
The second way of terminating the Idle mode is with an
external hardware reset, or an internal reset caused by
an overflow of the Watchdog Timer (T3). Since the
oscillator is still running, the hardware reset is required
to be active for two machine cycles (24 oscillator periods
but at least 2
μ
s) to complete the reset operation.
15.1.2
P
OWER
-
DOWN MODE
The instruction that sets PCON.1 is the last executed prior
to going into the Power-down mode. Once in Power-down
mode, the oscillator is stopped. Only the contents of the
on-chip RAM are preserved. The Special Function
Registers are not saved. A hardware reset is the only way
of exiting the Power-down mode.
In the Power-down mode, V
DD
may be reduced to
minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.
The status of the external pins during Power-down mode
is shown in Table 33. If the Power-down mode is activated
while in external program memory, the port data that is
held in the Special Function Register P2 is restored to
Port 2. If the data is a logic 1, the port pin is held HIGH
during the Power-down mode by the strong pull-up
transistor p1 (see Fig.7).
Table 33
Status of external pins during Idle and Power-down modes
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PWM0
Idle
internal
external
internal
external
1
1
0
0
1
1
0
0
port data
floating
port data
floating
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
1
1
1
1
Power-down
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