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參數(shù)資料
| 型號(hào)： | P80C562EFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大?。?/td> | 299K |
| 代理商： | P80C562EFA |
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1997 Apr 08
17
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
11.2
ADC Control Register (ADCON)
Table 9
ADC Control Register (SFR address C5H)
Table 10
Description of ADCON bits
Table 11
Function of ADCI and ADCS bits
7
6
5
4
3
2
1
0
ADEX
ADCI
ADCS
AADR2
AADR1
AADR0
BIT
SYMBOL
ADEX
DESCRIPTION
7
6
5
These two bits are reserved.
Enable external start:
start of conversion by STADC. If ADEX = 0, then conversion
can not be started externally by STADC (only by software by setting ADCS).
If ADEX = 1, then conversion can be started externally by a rising edge on STADC or by
software.
ADC interrupt flag:
this flag is set when an analog-to-digital conversion result is ready
to be read. An interrupt is invoked if it is enabled. The flag must be cleared by the
interrupt service routine. While this flag is set, the ADC cannot start a new conversion.
ADCI cannot be set by software.
ADC start and status:
setting this bit starts an ADC conversion. It may be set by
software or by the external signal STADC. The ADC logic ensures that this signal is
HIGH while the ADC is busy. On completion of the conversion, ADCS is reset
immediately after the interrupt flag has been set. ADCS can not be reset by software nor
can a new conversion be started if either ADCS or ADCI is HIGH.
Analog input select:
these three bits are used to select one of the eight analog inputs
of Port 5, for conversion. A selection can only be made when ADCI and ADCS are both
LOW. AADR2 is the most significant bit (e.g. 100 selects the ADC4 analog input
channel).
4
ADCI
3
ADCS
2
1
0
AADR.2
AADR.1
AADR.0
ADCI
ADCS
OPERATION
0
0
1
1
0
1
0
1
ADC not busy, a conversion can be started.
ADC busy, start of a new conversion is blocked.
Conversion completed; start of a new conversion is blocked.
Intermediate status for a maximum of one machine cycle before conversion is
completed.
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