參數(shù)資料
型號(hào)： P80C557E6
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller(單片8位微控制器)
中文描述： 單芯片8位微控制器（單片8位微控制器）
文件頁數(shù)： 37/64頁
文件大小： 476K
代理商： P80C557E6
Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
37
The polling cycle is repeated with every machine cycle, and the
values polled are the values present at S5P2 of the previous
machine cycle. Note that if an interrupt flag is active but is not being
responded to because of one of the above conditions, and if the flag
is inactive when the blocking condition is removed, then the blocked
interrupt will not be serviced. Thus, the fact that the interrupt flag
was once active but not serviced is not remembered. Every polling
cycle is new.
The processor acknowledges an interrupt request by executing a
hardware-generated LCALL to the appropriate service routine. In
some cases it also clears the flag which generated the interrupt, and
in others it does not. It clears the Timer 0, Timer 1, and external
interrupt flags. An external interrupt flag (IE0 or IE1) is cleared only if
it was transition-activated. All other interrupt flags are not cleared by
hardware and must be cleared by the software. The LCALL pushes
the contents of the program counter on to the stack (but it does not
save the PSW) and reloads the PC with an address that depends on
the source of the interrupt being vectored to as shown in Table 38.
Execution proceeds from the vector address until the RETI
instruction is encountered. The RETI instruction clears the “priority
level active” flip-flop that was set when this interrupt was
acknowledged. It then pops the top two bytes from the stack and
reloads the program counter. Execution of the in– terrupted program
continues from where it was interrupted.
Figure 35. Interrupt enable register (IEN0).
7
6
5
4
3
2
1
0
IEN0 (A8H)
EA
EAD
ES1
ES0
ET1
EX1
ET0
EX0
Table 33.
Description of IEN0 bits
SYMBOL
BIT
FUNCTION
EA
IEN0.7
Global enable/disable control
0 =
No interrupt is enabled
1 =
Any individually enabled interrupt will be accepted
EAD
IEN0.6
Enable ADC interrupt
Enable SIO1 (I
2
C) interrupt
ES1
IEN0.5
ES0
IEN0.4
Enable SIO0 (UART) interrupt
ET1
IEN0.3
Enable Timer 1 interrupt
EX1
IEN0.2
Enable External interrupt 1 / Seconds interrupt
ET0
IEN0.1
Enable Timer 0 interrupt
EX0
IEN0.0
Enable External interrupt 0
Figure 36. Interrupt enable register (IEN1).
7
6
5
4
3
2
1
0
IEN1 (E8H)
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
Table 34.
Description of IEN1 bits
SYMBOL
BIT
FUNCTION
ET2
IEN1.7
Enable T2 overflow interrupt(s)
ECM2
IEN1.6
Enable T2 comparator 2 interrupt
ECM1
IEN1.5
Enable T2 comparator 1 interrupt
ECM0
IEN1.4
Enable T2 comparator 0 interrupt
ECT3
IEN1.3
Enable T2 capture register 3 interrupt
ECT2
IEN1.2
Enable T2 capture register 2 interrupt
ECT1
IEN1.1
Enable T2 capture register 1 interrupt
ECT0
IEN1.0
Enable T2 capture register 0 interrupt
If the enable bit is 0, then the interrupt is disabled, if the enable bit is 1, then the interrupt is enabled.
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