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| 型號： | ORT82G5-3FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 91/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
73
Recommended Board-level Clocking for the ORT42G5 and ORT82G5
Option 1: Asynchronous Reference Clocks Between Rx and Tx Devices
Each board that uses the ORT42G5 or ORT82G5 as a transmit or receive device will have its own local reference
clock as shown in Figure 37. Figure 37 shows the ORT82G5 device on the switch card receiving data on two of its
channels from a separate source. Data tx1 is transmitted from a tx device with refclk1 as the reference clock and
Data tx2 is transmitted from a tx device with refclk2 as the reference clock. Receive channel AA locks to the incom-
ing data tx1 and receive channel AB locks to the incoming data tx2.
The advantage of this clocking scheme is the fact that it is not necessary to distribute a reference clock (typically
156 MHz for 10GE and 155.52 MHz for OC-192 applications) across a backplane.
Figure 37. Asynchronous Clocking Between Rx and Tx Devices
Option 2: Synchronous Reference Clocks to Rx and Tx Devices
In this type of clocking, a single reference clock is distributed to all receive and transmit devices in a system
(Figure 38). This distributed clocking scheme will permit maximum exibility in the usage of transmit and receive
channels in the current silicon such as:
All transmit and receive channels can be used within any quad in receive channel alignment or alignment bypass
mode.
In channel alignment mode, each receive channel operates on its own independent clock domain.
30A02
[0:1]
RX_FIFO_MIN
00
MSb’s for the threshold for low address in RX_FIFOs. RX_FIFO_MIN, Bit
1 is MSb. Useful values for RX_FIFO_MIN [0:4] are 0 to 17(decimal).
[2]
FMPU_RESYNC8
Resynchronizes all 8 channels when it transitions from 0 to 1. Status is a
0 on device reset.
[3:7]
—
Reserved for future use.
Common Status Registers xx=[AA,...,BD]
30A03
[0]
SYNC8_OVFL
00
Read-Only Multi-Channel Overow Status. When SYNC8_OVFL=1,
8-channel synchronization FIFO overow has occurred.
SYNC8_OVFL=0 on device reset.
[1]
SYNC8_OOS
Read-Only Multi-Channel Out-Of-Sync Status. When SYNC8_OOS=1,
8-channel synchronization has failed. SYNC8_OOS=0 on device reset.
[2:7]
Reserved for future use.
Table 30. ORT82G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
REFCLK 1
PORT CARD #1
PORT CARD #2
TX1
TX2
BACKPLANE
AC
AD
SWITCH
CARD
REFCLK 2
REFCLK 3
ORT42G5
or
ORT82G5
ORT42G5
or
ORT82G5
ORT42G5
or
ORT82G5
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| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
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