參數(shù)資料
型號： ORT82G5-3FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 48/119頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
34
Embedded Core/FPGA Interface
This block provides the data formatting and receive data and clock signal transfers between the Embedded Core
and the FPGA Logic. There are also control and status registers in the FPGA portion of the chip which contain bits
to control the receive logic and to record status. These are described in later sections of this data sheet and com-
municate with the core using the System Bus.
The demultiplexed, receive word outputs to the FPGA are shown in Figure 6. These are each 40 bits wide. There
are eight of these interfaces, one for each SERDES channel. Each consist of four groups of 10-bit data or four
groups of decoded information depending on setting of 8b10bR_xx control register bits.
Each 10-bit group of decoded information includes 8 bits of data and a 1 bit K_CTRL indicator derived from the
received data and a tenth bit of status information. The function of the tenth bit varies from group to group and
includes
code
violation,
Out
of
Synchronization
(OOS)
indicators
and
the
CH24_SYNC24_xx
and
CH248_SYNC_xx status bits. CH24_SYNC or CH248_SYNC_xx indicates the status of multi-channel alignment of
channel xx and are high when the count for the multi-channel alignment block reaches zero regardless of whether
or not multi-channel alignment is successful. The mapping of the 10-bit groups to the MRWD_xx[39:0] bits output to
the FPGA logic is summarized in Table 8. The various functions of the bits that vary from channel to channel, i.e.,
bits 29 and 19, are also described in Table 9 and Table 10.
Table 8. Denition of Bits of MRWDxx[39:0]
Bit Index
8b10bR=0
8b10bR=1
NOCHALGN[A:B]=1
CV_SELxx=0
NOCHALGN[A:B]=1
CV_SELxx=1
NOCHALGN[A:B]=0
CV_SELxx=1
39
bit 9 of 10-bit data 3
CV_xx3, code violation, byte 3
38
bit 8 of 10-bit data 3
K_CTRL for byte 3
37
bit 7 of 10-bit data 3
bit 7 of byte3
36
bit 6 of 10-bit data 3
bit 6 of byte 3
35
bit 5 of 10-bit data 3
bit 5 of byte 3
34
bit 4 of 10-bit data 3
bit 4 of byte 3
33
bit 3 of 10-bit data 3
bit 3 of byte 3
32
bit 2 of 10-bit data 3
bit 2 of byte 3
31
bit 1of 10-bit data 3
bit 1 of byte 3
30
bit 0 of 10-bit data 3
bit 0 of byte 3
29
bit 9 of 10-bit data 2
CV_xx2, code violation, byte 2
28
bit 8 of 10-bit data 2
K_CTRL for byte 2
27
bit 7 of 10-bit data 2
bit 7 of byte 2
26
bit 6 of 10-bit data 2
bit 6 of byte 2
25
bit 5 of 10-bit data 2
bit 5 of byte 2
24
bit 4 of 10-bit data 2
bit 4 of byte 2
23
bit 3 of 10-bit data 2
bit 3 of byte 2
22
bit 2 of 10-bit data 2
bit 2 of byte 2
21
bit 1 of 10-bit data 2
bit 1 of byte 2
20
bit 0 of 10-bit data 2
bit 0 of byte 2
19
bit 9 of 10-bit data 1
CV_xx1, code violation, byte 1
18
bit 8 of 10-bit data 1
K_CTRL for byte 1
17
bit 7 of 10-bit data 1
bit 7 of byte 1
16
bit 6 of 10-bit data 1
bit 6 of byte 1
15
bit 5 of 10-bit data 1
bit 5 of byte 1
14
bit 4 of 10-bit data 1
bit 4 of byte 1
13
bit 3 of 10-bit data 1
bit 3 of byte 1
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ORT82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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ORT8850 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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