參數(shù)資料
型號(hào)： ORT82G5-1FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 80/119頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
63
Control Registers (Read/Write), xx=[AC, AD, BC or BD]
30800 - Ax
30900 - Bx
[0]
—
00
Reserved for future use
[1]
—
Reserved for future use
[2]
ENBYSYNC_xC
ENBYSYNC_xC= 1 Enables Receiver Byte Synchronization for Channel
xC. ENBYSYNC_xC = 0 on device reset.
[3]
ENBYSYNC_xD
ENBYSYNC_xD = 1 Enables Receiver Byte Synchronization for Channel
xA. ENBYSYNC_xD = 0 on device reset.
[4]
—
Reserved for future use
[5]
—
Reserved for future use
[6]
LCKREFN_xC
LCKREFN_xC = 0 Locks the receiver PLL to reference clock for Channel
xC.
LCKREFN_xC =1 = Locks the receiver to data for Channel xx.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xC = 0 on device reset.
[7]
LCKREFN_xD
LCKREFN_xD = 0 Locks the receiver PLL to reference clock for Channel
xD.
LCKREFN_xD =1 = Locks the receiver to data for Channel xA.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xD = 0 on device reset.
30801 - Ax
30901 - Bx
[0]
—
00
Reserved for future use
[1]
—
Reserved for future use
[2]
LOOPENB_xC
Enable Loopback Mode for Channel xC. When LOOPEN_xC=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xC=0 on device reset.
[3]
LOOPENB_xD
Enable Loopback Mode for Channel xD. When LOOPEN_xD=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xD=0 on device reset.
[4]
—
Reserved for future use
[5]
—
Reserved for future use
[6]
NOWDALIGN_xC
Word Align Disable Bit. When NOWDALIGN_xC=1, receiver word align-
ment is disabled for Channel xC. NOWDALIGN_xC=0 on device reset.
[7]
NOWDALIGN_xD
Word Align Disable Bit. When NOWDALIGN_xD=1, receiver word align-
ment is disabled for Channel xD. NOWDALIGN_xD=0 on device reset.
Table 28. ORT42G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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ORT82G5-1FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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