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| 型號(hào)： | ORT82G5-1FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 79/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
62
SERDES Common Transmit and Receive Channel Conguration Registers (Read/Write), xx = [AC, AD, BC or BD]
30024 - AC
30034 - AD
30124 - BC
30134 - BD
[0]
Reserved
See
Bit
Desc.
Reserved, must be 0. Set to 0 on device reset.
[1]
MASK_xx
Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1,
the transmit and receive alarms of a channel are prevented from gener-
ating an interrupt (i.e., they are masked or disabled). The MASK_xx bit
overrides the individual alarm mask bits in the Alarm Mask Registers.
MASK_xx = 1 on device reset.
[2]
SWRST_xx
Transmit and Receive Software Reset Bit, Channel xx. When
SWRST_ss = 1, this bit provides the same function as the hardware
reset, except that all conguration register settings are unaltered. This is
not a self-clearing bit. Once set, this bit must be manually set and
cleared. SWRST = 0 on device reset.
[3:6] Not used
Not used
[7]
TESTEN_xx
Transmit and Receive Test Enable Bit, Channel xx. When TESTEN_xx =
1, the transmit and receive sections are placed in test mode. The
TestMode_[A:B][4:0] bits in the Global Control Registers specify the par-
ticular test, and must also be set.
Note: When the global test enable bit GTESTEN_[A:B] = 0, the individual
channel test enable bits are used to selectively place a channel in test or
normal mode. When GTESTEN_[A:B] = 1, all channels in a block are set
to test mode regardless of their TESTEN setting. TESTEN_xx = 0 on
device reset.
SERDES Global Control Registers (Read Write) - Act on Both Channels in SERDES Block A or SERDES Block B.
30005 - A
30105 - B
[0]
Reserved
See
Bit
Desc.
Reserved, must be 0. Set to 0 on device reset.
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms
of both channels in the SERDES block are prevented from generating an
interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over-
rides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset.
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit provides the same function
as the hardware reset for the transmit and receive sections of both chan-
nels, except that the device conguration settings are not affected when
GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once set, this
bit must be manually set and cleared. The GSWRST_[A:B] bit overrides
the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device reset.
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of
the transmit hardware for both channels are powered down to conserve
power. The GPWRDNT_[A:B] bit overrides the individual PWRDNT_xx
bits. GPWRDNT_[A:B] = 0 on device reset.
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of
the receive hardware for both channels are powered down to conserve
power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx
bits. GPWRDNR_[A:B] = 0 on device reset.
[5]
Reserved
Reserved, 1 on device reset.
[6]
Not used
[7]
GTESTEN_[A:B]
Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and
receive sections of both channels are placed in test mode. The
GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits.
GTESTEN_[A:B] = 0 on device reset.
30006 - A
30106 - B
00
Test Mode - See Test Mode section for settings
[5]
Not used
[6:7] Reserved
Reserved
Table 28. ORT42G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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