- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄11733 > ORT82G5-1FN680C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ORT82G5-1FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 54/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)當(dāng)前第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
4
High-speed SERDES with programmable serial data rates over the range 0.6 to 3.7 Gbps. Operation has been
demonstrated on design tolerance devices at 3.7 Gbps across 26 in. of FR-4 backplane and at 3.125 Gbps
across 40 in. of FR-4 backplane across temperature and voltage specications.
Asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock
per block channels (separate PLL per channel).
Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control
registers.
Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application.
Transmit preemphasis (programmable) for improved receive data eye opening.
32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic.
Provides a 10 Gbps backplane interface to switch fabric. Also supports multiple port cards at 2.5 Gbps.
3.125 Gbps SERDES compliant with XAUI serial data specication for 10 G Ethernet applications with protec-
tion.
IEEE 802.3ae compliant XAUI transceiver. Includes embedded IEEE 802.3ae-based XAUI link state machine.
Compliant to FC-0 specication for 1 Gbps, 2Gbps, 10 Gbps (FC-XAUI) modes. Includes Fibre Channel link state
machine.
High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
clocks.
SERDES has low-power CML buffers. Support for 1.5V/1.8V I/Os. Allows use with optical transceiver, coaxial
copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4.
Power down option of SERDES HSI receiver or transmitter on a per-channel basis.
Automatic lock to reference clock in the absence of valid receive data.
High-speed and low-speed loopback test modes.
Requires no external component for clock recovery and frequency synthesis.
SERDES characterization pins available to control/monitor the internal interface to one SERDES block
(ORT82G5 only).
SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating
state.
Built-in boundary scan (IEEE
1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES
interface.
FIFOs can align incoming data either across all eight channels (ORT82G5 only), across one or two groups of
four channels, or across two or four groups of two channels. Alignment is done either using comma characters or
by using the /A/ character in XAUI mode. Optionally, the alignment FIFOs can be bypassed for asynchronous
operation between channels. (Each channel includes its own clock and frame pulse or comma detect.)
Addition of two 4K x 36 dual-port RAMs with access to the programmable logic.
The ORT82G5 is pinout compatible to the ORCA ORSO82G5 SONET backplane driver FPSC. The ORT42G5 is
pin compatible to the ORSO42G5.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| MSP430F4793IPZ | IC MCU 16BIT 60KB FLASH 100LQFP |
| VE-J4B-IW-F3 | CONVERTER MOD DC/DC 95V 100W |
| PIC18F4510-I/ML | IC MCU FLASH 16KX16 44QFN |
| VE-J4B-IW-F2 | CONVERTER MOD DC/DC 95V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1FN680C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。