- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11733 > ORT82G5-1FN680C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPBGA PDF資料下載
參數(shù)資料
| 型號： | ORT82G5-1FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 67/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當前第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
51
Start Up Sequence for the ORT82G5
The following sequence is required by the ORT82G5 device. For information required for simulation that may be dif-
ferent than this sequence, see the ORT82G5 Design Kit.
1.
Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA conguration of the
device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN.
2.
Congure the following SERDES internal and external registers. Note that after device initialization, all alarm
and status bits should be read once to clear them. A subsequent read will provide the valid state. Set the fol-
lowing bits in register 30800:
– Bits LCKREFN_[AA:AD] to 1, which implies lock to data.
– Bits ENBYSYNC_[AA:AD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30801:
– Bits LOOPENB_[AA:AD] to 1 if high-speed serial loopback is desired.
Set the following bits in register 30900:
– Bits LCKREFN_[BA:BD] to 1 which implies lock to data.
– Bits ENBYSYNC_[BA:BD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30901:
– Bits LOOPENB_[BA:BD] to 1 if high-speed serial loopback is desired.
Set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132:
– TXHR set to 1 if TX half-rate is desired.
– 8B10BT set to 1
Set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133:
– RXHR Set to 1 if RX half-rate is desired.
– 8B10BR set to 1.
– LINKSM set to 1 if the Fibre Channel state machine is desired.
Assert GSWRST bit by writing two 1’s. Deassert GSWRST bit by writing two 0’s. Wait 3ms. If higher speed
serial loopback has been selected, the receive PLLs will use this time to lock to the new serial data.
Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130:
– LKI, PLL lock indicator. 1 indicates that PLL has achieved lock.
3. If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three
times:
– K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode.
– /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI
mode.
相關PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| MSP430F4793IPZ | IC MCU 16BIT 60KB FLASH 100LQFP |
| VE-J4B-IW-F3 | CONVERTER MOD DC/DC 95V 100W |
| PIC18F4510-I/ML | IC MCU FLASH 16KX16 44QFN |
| VE-J4B-IW-F2 | CONVERTER MOD DC/DC 95V 100W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復。