參數(shù)資料
型號(hào)： ORSO82G5-2FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 4/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
101
Table 36. Common Control Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
30A00
[0:1]
RCKSELB
00
“00” - Channel BA source for clock RCK78B
“01” - Channel BB source for clock RCK78B
“10” - Channel BC source for clock RCK78B
“11” - Channel BD source for clock RCK78B
Both
[2:3]
TCKSELB
“00” - Channel BA source for clock TCK78B
“01” - Channel BB source for clock TCK78B
“10” - Channel BC source for clock TCK78B
“11” - Channel BD source for clock TCK78B
Both
[4:5]
RCKSELA
“00” - Channel AA source for clock RCK78A
“01” - Channel AB source for clock RCK78A
“10” - Channel AC source for clock RCK78A
“11” - Channel AD source for clock RCK78A
Both
[6:7]
TCKSELA
“00” - Channel AA source for clock TCK78A
“01” - Channel AB source for clock TCK78A
“10” - Channel AC source for clock TCK78A
“11” - Channel AD source for clock TCK78A
Both
30A01
[0:2]
CELL_SIZE
00
Cell Size, Three bits to set cell size.
“000” - Cell size is 75 bytes,
“001” - Cell size is 79 bytes,
“010” - Cell size is 83 bytes,
“011” - Cell size is 91 bytes
These are the only supported cell sizes.
Cell
[3:7]
RX_FIFO_MIN
Set Minimum threshold value for alignment
FIFO in SONET mode. When the read address
for the FIFO is below this value at the time when
write address is zero, it indicates that the FIFO
is near overow. This event will go high only
once during a frame when a framing byte has
been detected by the aligner. The default
threshold value is “00000”.
SONET
30A02
0
TX_DISABLE_ON_RDI
00
Transmitter Disable on RDI (Detection), If
TX_DISABLE_ON_RDI = 1 - No cell data is
transmitted on a link in which a RDI has been
detected by the corresponding link’s receiver. If
this bit is set to 0, cell data will be transmitted on
a link irrespective of detection of a RDI.
Cell
[1:3]
RSVD
Reserved
—
4
SCHAR_ENA
SCHAR_ENA = 1 enables SERDES character-
ization of SERDES B. Refer to section
Factory
Test
5
SCHAR_TXSEL
SCHAR_TXSEL =1 is a Select Tx option which
will cause chip ports to directly control the SER-
DES low-speed transmit ports of one of the
channels selected by SCHAR_CHAN
Factory
Test
6:7
SCHAR_CHAN
“00” - Select channel BA to test
“01” - Select channel BB to test
“10” - Select channel BC to test
“11” - Select channel BD to test
Factory
Test
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參數(shù)描述
ORSO82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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