參數(shù)資料
型號(hào): ORSO82G5-2FN680C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 130/153頁
文件大小: 0K
描述: IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告: Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝: 24
系列: *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
78
Register Reset Conditions
The reset conditions for the registers vary depending on register type. See the tables and the accompanying text
for a description of the reset conditions.
Table 21. SERDES Alarm and Alarm Mask Register Descriptions – ORSO42G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Alarm Registers (Read Only) xx = [AC, AD, BC, BD]
30020 - AC
30030 - AD
30120 - BC
30130 - BD
[0]
RSVD
00
Reserved - May be non-zero
[1]
LKI_xx
Receive PLL Lock Indication, Channel xx.
LKI_xx = 1 indicates the receive PLL is locked.
Note that the PLL can either lock to the incom-
ing data or to RECLK_[A:B]. If the PLL is locked
to data and the data stream is terminated,
LKI_xx will go low until the PLL locks to
REFCLK_[A:B].
Both
[2:7]
RSVD
Reserved - May be non-zero
SERDES Alarm Mask Registers (Read/Write) xx = [AC, AD, BC, BD]
30021 - AC
30031 - AD
30121 - BC
30131 - BD
[0]
RSVD
FF
Reserved
[1]
MLKI_xx
Mask Receive PLL Lock Indication, Channel
MLKI_xx = 1 indicates LKI_xx is enabled
Both
[2:7]
RSVD
Reserved
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